dcm1.sym

来自「FPGA-CPLD_DesignTool(8-9-10)源代码」· SYM 代码 · 共 22 行

VERSION 5
BEGIN SYMBOL 
SYMBOLTYPE BLOCK
TIMESTAMP 2002 11 12 1 37 0
SYMPIN 0 -32 Input "CLKIN_IN"
SYMPIN 400 -32 Output "CLK0_OUT"
RECTANGLE N 64 -64 336 0 
BEGIN DISPLAY 200 -72 ATTR "SymbolName"
    ALIGNMENT BCENTER
    FONT 56 "Arial"
END DISPLAY
LINE N 64 -32 0 -32 
BEGIN DISPLAY 72 -32 PIN "CLKIN_IN" ATTR "PinName"
    FONT 24 "Arial"
END DISPLAY
LINE N 336 -32 400 -32 
BEGIN DISPLAY 328 -32 PIN "CLK0_OUT" ATTR "PinName"
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
END SYMBOL