stopwatch.par

来自「FPGA-CPLD_DesignTool(8-9-10)源代码」· PAR 代码 · 共 133 行

Release 5.1i - Par F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.


    ::  Thu Dec 19 18:12:21 2002


J:/eda/Xilinx/bin/nt/par.exe -w -ol 2 -t 1 stopwatch_map.ncd stopwatch.ncd
stopwatch.pcf 


Constraints file: stopwatch.pcf

Loading device database for application par from file "stopwatch_map.ncd".
   "stopwatch" is an NCD, version 2.37, device xc2v40, package fg256, speed -5
Loading device for application par from file '2v40.nph' in environment
J:/eda/Xilinx.
The STEPPING level for this design is 1.
Device speed data version:  ADVANCED 1.110 2002-07-03.


Resolved that IOB <reset> must be placed at site A5.


Device utilization summary:

   Number of External IOBs            27 out of 88     30%
      Number of LOCed External IOBs    1 out of 27      3%

   Number of SLICEs                   31 out of 256    12%

   Number of BUFGMUXs                  1 out of 16      6%
   Number of DCMs                      1 out of 4      25%



Overall effort level (-ol):   2 (set by user)
Placer effort level (-pl):    2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    2 (set by user)


Phase 1.1
Phase 1.1 (Checksum:989788) REAL time: 2 secs 

Phase 3.23
....................................
Phase 3.23 (Checksum:989682) REAL time: 2 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 2 secs 

Phase 6.8
.....
Phase 6.8 (Checksum:9910d7) REAL time: 2 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 2 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 2 secs 

Phase 9.24
Phase 9.24 (Checksum:55d4a77) REAL time: 2 secs 

Writing design to file stopwatch.ncd.

Total REAL time to placer completion: 2 secs 
Total CPU time to placer completion: 1 secs 


Starting Router          REAL time: 2 secs 

Phase 1: 266 unrouted;       REAL time: 2 secs 

Phase 2: 241 unrouted;       REAL time: 2 secs 

Phase 3: 71 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 

Finished Router          REAL time: 2 secs 

Total REAL time to router completion: 2 secs 
Total CPU time to router completion: 1 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Max Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|           clk_int          |  Global  |   15   |  0.011     |  0.570      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The Score for this design is: 5084


The Number of signals not completely routed for this design is: 0

   The Average Connection Delay for this design is:        0.614 ns
   The Maximum Pin Delay is:                               1.726 ns
   The Average Connection Delay on the 10 Worst Nets is:   1.161 ns

   Listing Pin Delays by value: (ns)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         222          44           0           0           0           0


All signals are completely routed.

Total REAL time to par completion: 2 secs 
Total CPU time to par completion: 1 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file stopwatch.ncd.


PAR done.