📄 cnt60.vhf
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-- Vhdl model created from schematic J:\eda\Xilinx\virtex2\data\drawing\ftce.sch - Thu Dec 19 18:12:07 2002
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-- synopsys translate_off
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
-- synopsys translate_on
ENTITY FTCE_MXILINX_cnt60 IS
PORT ( C : IN STD_LOGIC;
CE : IN STD_LOGIC;
CLR : IN STD_LOGIC;
T : IN STD_LOGIC;
Q : OUT STD_LOGIC);
end FTCE_MXILINX_cnt60;
ARCHITECTURE SCHEMATIC OF FTCE_MXILINX_cnt60 IS
SIGNAL Q_DUMMY : STD_LOGIC;
SIGNAL TQ : STD_LOGIC;
ATTRIBUTE BOX_TYPE : STRING;
ATTRIBUTE INIT : STRING ;
ATTRIBUTE RLOC : STRING ;
ATTRIBUTE INIT OF I_36_35 : LABEL IS "0";
ATTRIBUTE RLOC OF I_36_35 : LABEL IS "X0Y0";
COMPONENT FDCE
-- synopsys translate_off
GENERIC( INIT : BIT := '0' );
-- synopsys translate_on
PORT ( C : IN STD_LOGIC;
CE : IN STD_LOGIC;
CLR : IN STD_LOGIC;
D : IN STD_LOGIC;
Q : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE BOX_TYPE OF FDCE : COMPONENT IS "BLACK_BOX";
COMPONENT XOR2
PORT ( I0 : IN STD_LOGIC;
I1 : IN STD_LOGIC;
O : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE BOX_TYPE OF XOR2 : COMPONENT IS "BLACK_BOX";
BEGIN
Q <= Q_DUMMY;
I_36_35 : FDCE
-- synopsys translate_off
GENERIC MAP ( INIT => '0' )
-- synopsys translate_on
PORT MAP (C=>C, CE=>CE, CLR=>CLR, D=>TQ, Q=>Q_DUMMY);
I_36_32 : XOR2
PORT MAP (I0=>T, I1=>Q_DUMMY, O=>TQ);
END SCHEMATIC;
-- Vhdl model created from schematic J:\eda\Xilinx\virtex2\data\drawing\cb4ce.sch - Thu Dec 19 18:12:07 2002
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-- synopsys translate_off
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
-- synopsys translate_on
ENTITY CB4CE_MXILINX_cnt60 IS
PORT ( C : IN STD_LOGIC;
CE : IN STD_LOGIC;
CLR : IN STD_LOGIC;
CEO : OUT STD_LOGIC;
Q0 : OUT STD_LOGIC;
Q1 : OUT STD_LOGIC;
Q2 : OUT STD_LOGIC;
Q3 : OUT STD_LOGIC;
TC : OUT STD_LOGIC);
end CB4CE_MXILINX_cnt60;
ARCHITECTURE SCHEMATIC OF CB4CE_MXILINX_cnt60 IS
SIGNAL Q0_DUMMY : STD_LOGIC;
SIGNAL Q1_DUMMY : STD_LOGIC;
SIGNAL Q2_DUMMY : STD_LOGIC;
SIGNAL Q3_DUMMY : STD_LOGIC;
SIGNAL T2 : STD_LOGIC;
SIGNAL T3 : STD_LOGIC;
SIGNAL TC_DUMMY : STD_LOGIC;
SIGNAL XLXN_1 : STD_LOGIC;
ATTRIBUTE BOX_TYPE : STRING;
ATTRIBUTE U_SET : STRING ;
ATTRIBUTE U_SET OF I_Q0 : LABEL IS "I_Q0_0";
ATTRIBUTE U_SET OF I_Q1 : LABEL IS "I_Q1_1";
ATTRIBUTE U_SET OF I_Q2 : LABEL IS "I_Q2_2";
ATTRIBUTE U_SET OF I_Q3 : LABEL IS "I_Q3_3";
COMPONENT AND2
PORT ( I0 : IN STD_LOGIC;
I1 : IN STD_LOGIC;
O : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE BOX_TYPE OF AND2 : COMPONENT IS "BLACK_BOX";
COMPONENT AND3
PORT ( I0 : IN STD_LOGIC;
I1 : IN STD_LOGIC;
I2 : IN STD_LOGIC;
O : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE BOX_TYPE OF AND3 : COMPONENT IS "BLACK_BOX";
COMPONENT AND4
PORT ( I0 : IN STD_LOGIC;
I1 : IN STD_LOGIC;
I2 : IN STD_LOGIC;
I3 : IN STD_LOGIC;
O : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE BOX_TYPE OF AND4 : COMPONENT IS "BLACK_BOX";
COMPONENT FTCE_MXILINX_cnt60
PORT ( C : IN STD_LOGIC;
CE : IN STD_LOGIC;
CLR : IN STD_LOGIC;
T : IN STD_LOGIC;
Q : OUT STD_LOGIC);
END COMPONENT;
COMPONENT VCC
PORT ( P : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE BOX_TYPE OF VCC : COMPONENT IS "BLACK_BOX";
BEGIN
Q0 <= Q0_DUMMY;
Q1 <= Q1_DUMMY;
Q2 <= Q2_DUMMY;
Q3 <= Q3_DUMMY;
TC <= TC_DUMMY;
I_36_33 : AND2
PORT MAP (I0=>Q1_DUMMY, I1=>Q0_DUMMY, O=>T2);
I_36_67 : AND2
PORT MAP (I0=>CE, I1=>TC_DUMMY, O=>CEO);
I_36_32 : AND3
PORT MAP (I0=>Q2_DUMMY, I1=>Q1_DUMMY, I2=>Q0_DUMMY, O=>T3);
I_36_31 : AND4
PORT MAP (I0=>Q3_DUMMY, I1=>Q2_DUMMY, I2=>Q1_DUMMY, I3=>Q0_DUMMY,
O=>TC_DUMMY);
I_Q0 : FTCE_MXILINX_cnt60
PORT MAP (C=>C, CE=>CE, CLR=>CLR, T=>XLXN_1, Q=>Q0_DUMMY);
I_Q1 : FTCE_MXILINX_cnt60
PORT MAP (C=>C, CE=>CE, CLR=>CLR, T=>Q0_DUMMY, Q=>Q1_DUMMY);
I_Q2 : FTCE_MXILINX_cnt60
PORT MAP (C=>C, CE=>CE, CLR=>CLR, T=>T2, Q=>Q2_DUMMY);
I_Q3 : FTCE_MXILINX_cnt60
PORT MAP (C=>C, CE=>CE, CLR=>CLR, T=>T3, Q=>Q3_DUMMY);
I_36_58 : VCC
PORT MAP (P=>XLXN_1);
END SCHEMATIC;
-- Vhdl model created from schematic J:\eda\Xilinx\virtex2\data\drawing\cd4ce.sch - Thu Dec 19 18:12:07 2002
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-- synopsys translate_off
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
-- synopsys translate_on
ENTITY CD4CE_MXILINX_cnt60 IS
PORT ( C : IN STD_LOGIC;
CE : IN STD_LOGIC;
CLR : IN STD_LOGIC;
CEO : OUT STD_LOGIC;
Q0 : OUT STD_LOGIC;
Q1 : OUT STD_LOGIC;
Q2 : OUT STD_LOGIC;
Q3 : OUT STD_LOGIC;
TC : OUT STD_LOGIC);
end CD4CE_MXILINX_cnt60;
ARCHITECTURE SCHEMATIC OF CD4CE_MXILINX_cnt60 IS
SIGNAL A03B : STD_LOGIC;
SIGNAL AO3A : STD_LOGIC;
SIGNAL AX1 : STD_LOGIC;
SIGNAL AX2 : STD_LOGIC;
SIGNAL D0 : STD_LOGIC;
SIGNAL D1 : STD_LOGIC;
SIGNAL D2 : STD_LOGIC;
SIGNAL D3 : STD_LOGIC;
SIGNAL OX3 : STD_LOGIC;
SIGNAL Q0_DUMMY : STD_LOGIC;
SIGNAL Q1_DUMMY : STD_LOGIC;
SIGNAL Q2_DUMMY : STD_LOGIC;
SIGNAL Q3_DUMMY : STD_LOGIC;
SIGNAL TC_DUMMY : STD_LOGIC;
ATTRIBUTE BOX_TYPE : STRING;
ATTRIBUTE INIT : STRING ;
ATTRIBUTE INIT OF I_Q0 : LABEL IS "0";
ATTRIBUTE INIT OF I_Q1 : LABEL IS "0";
ATTRIBUTE INIT OF I_Q2 : LABEL IS "0";
ATTRIBUTE INIT OF I_Q3 : LABEL IS "0";
COMPONENT AND2
PORT ( I0 : IN STD_LOGIC;
I1 : IN STD_LOGIC;
O : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE BOX_TYPE OF AND2 : COMPONENT IS "BLACK_BOX";
COMPONENT AND2B1
PORT ( I0 : IN STD_LOGIC;
I1 : IN STD_LOGIC;
O : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE BOX_TYPE OF AND2B1 : COMPONENT IS "BLACK_BOX";
COMPONENT AND3
PORT ( I0 : IN STD_LOGIC;
I1 : IN STD_LOGIC;
I2 : IN STD_LOGIC;
O : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE BOX_TYPE OF AND3 : COMPONENT IS "BLACK_BOX";
COMPONENT AND4B2
PORT ( I0 : IN STD_LOGIC;
I1 : IN STD_LOGIC;
I2 : IN STD_LOGIC;
I3 : IN STD_LOGIC;
O : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE BOX_TYPE OF AND4B2 : COMPONENT IS "BLACK_BOX";
COMPONENT FDCE
-- synopsys translate_off
GENERIC( INIT : BIT := '0' );
-- synopsys translate_on
PORT ( C : IN STD_LOGIC;
CE : IN STD_LOGIC;
CLR : IN STD_LOGIC;
D : IN STD_LOGIC;
Q : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE BOX_TYPE OF FDCE : COMPONENT IS "BLACK_BOX";
COMPONENT INV
PORT ( I : IN STD_LOGIC;
O : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE BOX_TYPE OF INV : COMPONENT IS "BLACK_BOX";
COMPONENT OR2
PORT ( I0 : IN STD_LOGIC;
I1 : IN STD_LOGIC;
O : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE BOX_TYPE OF OR2 : COMPONENT IS "BLACK_BOX";
COMPONENT XOR2
PORT ( I0 : IN STD_LOGIC;
I1 : IN STD_LOGIC;
O : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE BOX_TYPE OF XOR2 : COMPONENT IS "BLACK_BOX";
BEGIN
Q0 <= Q0_DUMMY;
Q1 <= Q1_DUMMY;
Q2 <= Q2_DUMMY;
Q3 <= Q3_DUMMY;
TC <= TC_DUMMY;
I_36_88 : AND2
PORT MAP (I0=>Q3_DUMMY, I1=>Q0_DUMMY, O=>AO3A);
I_36_77 : AND2
PORT MAP (I0=>Q0_DUMMY, I1=>Q1_DUMMY, O=>AX2);
I_36_99 : AND2
PORT MAP (I0=>CE, I1=>TC_DUMMY, O=>CEO);
I_36_81 : AND2B1
PORT MAP (I0=>Q3_DUMMY, I1=>Q0_DUMMY, O=>AX1);
I_36_70 : AND3
PORT MAP (I0=>Q2_DUMMY, I1=>Q0_DUMMY, I2=>Q1_DUMMY, O=>A03B);
I_36_105 : AND4B2
PORT MAP (I0=>Q2_DUMMY, I1=>Q1_DUMMY, I2=>Q0_DUMMY, I3=>Q3_DUMMY,
O=>TC_DUMMY);
I_Q0 : FDCE
-- synopsys translate_off
GENERIC MAP ( INIT => '0' )
-- synopsys translate_on
PORT MAP (C=>C, CE=>CE, CLR=>CLR, D=>D0, Q=>Q0_DUMMY);
I_Q1 : FDCE
-- synopsys translate_off
GENERIC MAP ( INIT => '0' )
-- synopsys translate_on
PORT MAP (C=>C, CE=>CE, CLR=>CLR, D=>D1, Q=>Q1_DUMMY);
I_Q2 : FDCE
-- synopsys translate_off
GENERIC MAP ( INIT => '0' )
-- synopsys translate_on
PORT MAP (C=>C, CE=>CE, CLR=>CLR, D=>D2, Q=>Q2_DUMMY);
I_Q3 : FDCE
-- synopsys translate_off
GENERIC MAP ( INIT => '0' )
-- synopsys translate_on
PORT MAP (C=>C, CE=>CE, CLR=>CLR, D=>D3, Q=>Q3_DUMMY);
I_36_83 : INV
PORT MAP (I=>Q0_DUMMY, O=>D0);
I_36_75 : OR2
PORT MAP (I0=>AO3A, I1=>A03B, O=>OX3);
I_36_86 : XOR2
PORT MAP (I0=>Q1_DUMMY, I1=>AX1, O=>D1);
I_36_78 : XOR2
PORT MAP (I0=>Q2_DUMMY, I1=>AX2, O=>D2);
I_36_73 : XOR2
PORT MAP (I0=>Q3_DUMMY, I1=>OX3, O=>D3);
END SCHEMATIC;
-- Vhdl model created from schematic cnt60.sch - Thu Dec 19 18:12:07 2002
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-- synopsys translate_off
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
-- synopsys translate_on
ENTITY cnt60 IS
PORT ( ce : IN STD_LOGIC;
clk : IN STD_LOGIC;
clr : IN STD_LOGIC;
lsbsec : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
msbsec : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
end cnt60;
ARCHITECTURE SCHEMATIC OF cnt60 IS
SIGNAL XLXN_15 : STD_LOGIC;
SIGNAL XLXN_16 : STD_LOGIC;
SIGNAL XLXN_24 : STD_LOGIC;
SIGNAL XLXN_26 : STD_LOGIC;
SIGNAL XLXN_27 : STD_LOGIC;
SIGNAL XLXN_8 : STD_LOGIC;
SIGNAL XLXN_9 : STD_LOGIC;
SIGNAL msbsec_DUMMY : STD_LOGIC_VECTOR (3 DOWNTO 0);
ATTRIBUTE BOX_TYPE : STRING;
ATTRIBUTE U_SET : STRING ;
ATTRIBUTE U_SET OF XLXI_3 : LABEL IS "XLXI_3_5";
ATTRIBUTE U_SET OF XLXI_2 : LABEL IS "XLXI_2_4";
COMPONENT AND2
PORT ( I0 : IN STD_LOGIC;
I1 : IN STD_LOGIC;
O : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE BOX_TYPE OF AND2 : COMPONENT IS "BLACK_BOX";
COMPONENT AND4
PORT ( I0 : IN STD_LOGIC;
I1 : IN STD_LOGIC;
I2 : IN STD_LOGIC;
I3 : IN STD_LOGIC;
O : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE BOX_TYPE OF AND4 : COMPONENT IS "BLACK_BOX";
COMPONENT CB4CE_MXILINX_cnt60
PORT ( C : IN STD_LOGIC;
CE : IN STD_LOGIC;
CLR : IN STD_LOGIC;
CEO : OUT STD_LOGIC;
Q0 : OUT STD_LOGIC;
Q1 : OUT STD_LOGIC;
Q2 : OUT STD_LOGIC;
Q3 : OUT STD_LOGIC;
TC : OUT STD_LOGIC);
END COMPONENT;
COMPONENT CD4CE_MXILINX_cnt60
PORT ( C : IN STD_LOGIC;
CE : IN STD_LOGIC;
CLR : IN STD_LOGIC;
CEO : OUT STD_LOGIC;
Q0 : OUT STD_LOGIC;
Q1 : OUT STD_LOGIC;
Q2 : OUT STD_LOGIC;
Q3 : OUT STD_LOGIC;
TC : OUT STD_LOGIC);
END COMPONENT;
COMPONENT INV
PORT ( I : IN STD_LOGIC;
O : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE BOX_TYPE OF INV : COMPONENT IS "BLACK_BOX";
COMPONENT OR2
PORT ( I0 : IN STD_LOGIC;
I1 : IN STD_LOGIC;
O : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE BOX_TYPE OF OR2 : COMPONENT IS "BLACK_BOX";
BEGIN
msbsec <= msbsec_DUMMY;
XLXI_1 : AND2
PORT MAP (I0=>XLXN_24, I1=>XLXN_27, O=>XLXN_26);
XLXI_7 : AND2
PORT MAP (I0=>ce, I1=>XLXN_8, O=>XLXN_27);
XLXI_6 : AND4
PORT MAP (I0=>XLXN_15, I1=>msbsec_DUMMY(2), I2=>XLXN_16,
I3=>msbsec_DUMMY(0), O=>XLXN_24);
XLXI_3 : CB4CE_MXILINX_cnt60
PORT MAP (C=>clk, CE=>XLXN_27, CLR=>XLXN_9, CEO=>open,
Q0=>msbsec_DUMMY(0), Q1=>msbsec_DUMMY(1), Q2=>msbsec_DUMMY(2),
Q3=>msbsec_DUMMY(3), TC=>open);
XLXI_2 : CD4CE_MXILINX_cnt60
PORT MAP (C=>clk, CE=>ce, CLR=>clr, CEO=>open, Q0=>lsbsec(0),
Q1=>lsbsec(1), Q2=>lsbsec(2), Q3=>lsbsec(3), TC=>XLXN_8);
XLXI_5 : INV
PORT MAP (I=>msbsec_DUMMY(1), O=>XLXN_16);
XLXI_8 : INV
PORT MAP (I=>msbsec_DUMMY(3), O=>XLXN_15);
XLXI_4 : OR2
PORT MAP (I0=>XLXN_26, I1=>clr, O=>XLXN_9);
END SCHEMATIC;
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