wtut_sc.ptf

来自「FPGA-CPLD_DesignTool(8-9-10)源代码」· PTF 代码 · 共 13 行

[decode]
Synthesize=true
[stopwatch]
Design Entry Utilities=true
Implement Design=false
Map=true
Place & Route=true
Synthesize=false
Translate=true
User Constraints=false
[stopwatch_tb.vhd]
ModelSim Simulator=false