outs3.sym

来自「FPGA-CPLD_DesignTool(8-9-10)源代码」· SYM 代码 · 共 24 行

VERSION 5
BEGIN SYMBOL 
SYMBOLTYPE BLOCK
TIMESTAMP 2002 12 19 10 14 0
SYMPIN 0 -32 Input "inputs(9:0)"
SYMPIN 384 -32 Output "outs(9:0)"
BEGIN DISPLAY 192 -72 ATTR "SymbolName"
    ALIGNMENT BCENTER
    FONT 56 "Arial"
END DISPLAY
BEGIN DISPLAY 72 -32 PIN "inputs(9:0)" ATTR "PinName"
    FONT 24 "Arial"
END DISPLAY
BEGIN DISPLAY 312 -32 PIN "outs(9:0)" ATTR "PinName"
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
RECTANGLE N 64 -64 320 0 
LINE N 64 -32 0 -32 
RECTANGLE N 0 -44 64 -20 
LINE N 320 -32 384 -32 
RECTANGLE N 320 -44 384 -20 
END SYMBOL