stopwatch.syr

FPGA-CPLD_DesignTool(8-9-10)源代码

    -----------------------------------------------------------------------
    Summary:
	inferred   1 Finite State Machine(s).
Unit <stmach_v> synthesized.


Synthesizing Unit <outs3>.
    Related source file is J:/projects/ISE/ISEexamples/wtut_sc/outs3.vhf.
Unit <outs3> synthesized.


Synthesizing Unit <hex2led>.
    Related source file is J:/projects/ISE/ISEexamples/wtut_sc/hex2led.vhd.
    Found 16x7-bit ROM for signal <led>.
    Summary:
	inferred   1 ROM(s).
Unit <hex2led> synthesized.


Synthesizing Unit <decode>.
    Related source file is J:/projects/ISE/ISEexamples/wtut_sc/decode.vhd.
    Found 16x10-bit ROM for signal <one_hot>.
    Summary:
	inferred   1 ROM(s).
Unit <decode> synthesized.


Synthesizing Unit <dcm1>.
    Related source file is J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd.
Unit <dcm1> synthesized.


Synthesizing Unit <cnt60>.
    Related source file is J:/projects/ISE/ISEexamples/wtut_sc/cnt60.vhf.
Unit <cnt60> synthesized.


Synthesizing Unit <stopwatch>.
    Related source file is J:/projects/ISE/ISEexamples/wtut_sc/stopwatch.vhf.
Unit <stopwatch> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 3
  16x7-bit ROM                     : 2
  16x10-bit ROM                    : 1

=========================================================================

Optimizing FSM <FSM_0> with One-Hot encoding and d flip-flops.
=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "tenths.ngo" is up to date.
Loading core <tenths> for timing and area information for instance <tenths_t>.

Library "J:/eda/Xilinx/data/librtl.xst" Consulted

Optimizing unit <stopwatch> ...

Optimizing unit <outs3> ...

Optimizing unit <stmach_v> ...

Optimizing unit <cd4ce_mxilinx_cnt60> ...

Optimizing unit <ftce_mxilinx_cnt60> ...

Optimizing unit <cb4ce_mxilinx_cnt60> ...

Mapping all equations...
Loading device for application Xst from file '2v40.nph' in environment J:/eda/Xilinx.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block stopwatch, actual ratio is 11.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Output File Name               : stopwatch.ngr
Top Level Output File Name         : stopwatch
Output Format                      : NGC
Optimization Criterion             : Speed
Keep Hierarchy                     : NO
Macro Generator                    : macro+

Design Statistics
# IOs                              : 27

Macro Statistics :
# ROMs                             : 3
#      16x10-bit ROM               : 1
#      16x7-bit ROM                : 2

Cell Usage :
# BELS                             : 88
#      and2                        : 8
#      and2b1                      : 1
#      and3                        : 2
#      and4                        : 2
#      and4b2                      : 1
#      GND                         : 2
#      inv                         : 14
#      LUT2_L                      : 1
#      LUT3                        : 4
#      LUT4                        : 37
#      MUXCY                       : 3
#      or2                         : 2
#      vcc                         : 1
#      xor2                        : 7
#      XORCY                       : 3
# FlipFlops/Latches                : 20
#      FDC                         : 5
#      FDCE                        : 11
#      FDE                         : 2
#      FDP                         : 1
#      FDPE                        : 1
# Clock Buffers                    : 1
#      bufg                        : 1
# IO Buffers                       : 27
#      ibuf                        : 2
#      ibufg                       : 1
#      obuf                        : 24
# DCMs                             : 1
#      dcm                         : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v40fg256-5 

 Number of Slices:                      29  out of    256    11%  
 Number of Slice Flip Flops:            20  out of    512     3%  
 Number of 4 input LUTs:                42  out of    512     8%  
 Number of bonded IOBs:                 27  out of     88    30%  
 Number of GCLKs:                        1  out of     16     6%  
 Number of DCMs:                         1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | dcm1_t_dcm_inst:clk0   | 20    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 6.981ns (Maximum Frequency: 143.246MHz)
   Minimum input arrival time before clock: 2.736ns
   Maximum output required time after clock: 8.543ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               6.981ns (Levels of Logic = 5)
  Source:            stmach_t_sreg_ffd2
  Destination:       cnt60_t_xlxi_3/i_q2/i_36_35
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: stmach_t_sreg_ffd2 to cnt60_t_xlxi_3/i_q2/i_36_35
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:c->q              3   0.494   0.865  stmach_t_sreg_ffd2 (stmach_t_sreg_ffd2)
     LUT2_L:I0->LO         5   0.382   0.100  stmach_t_clkout1 (clken_int)
     and2:i0->o            6   0.382   1.032  xlxi_22 (xlxn_95)
     and2:i0->o            6   0.382   1.032  cnt60_t_xlxi_7 (cnt60_t_xlxn_27)
     and2:i1->o            1   0.382   0.360  cnt60_t_xlxi_1 (cnt60_t_xlxn_26)
     or2:i0->o             4   0.382   0.944  cnt60_t_xlxi_4 (cnt60_t_xlxn_9)
     begin scope: 'cnt60_t_xlxi_3'
     begin scope: 'i_q2'
     FDCE:clr                  0.244          i_36_35
    ----------------------------------------
    Total                      6.981ns (2.648ns logic, 4.333ns route)
                                       (37.9% logic, 62.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Offset:              2.736ns (Levels of Logic = 2)
  Source:            reset
  Destination:       stmach_t_sreg_ffd6
  Destination Clock: clk rising

  Data Path: reset to stmach_t_sreg_ffd6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     ibuf:i->o             1   0.718   0.360  xlxi_10 (xlxn_2)
     inv:i->o              6   0.382   1.032  xlxi_9 (xlxn_3)
     FDC:clr                   0.244          stmach_t_sreg_ffd6
    ----------------------------------------
    Total                      2.736ns (1.344ns logic, 1.392ns route)
                                       (49.1% logic, 50.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              8.543ns (Levels of Logic = 3)
  Source:            tenths_t/bu28
  Destination:       tenthsout<7>
  Source Clock:      clk rising

  Data Path: tenths_t/bu28 to tenthsout<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDPE:c->q            11   0.494   1.254  bu28 (q<0>)
     end scope: 'tenths_t'
     LUT4:i0->o            1   0.382   0.360  decode_t_mrom_one_hot_inst_lut4_71 (xlxn_36<7>)
     inv:i->o              1   0.382   0.360  out3_t_i14 (out3_t_xlxn_14)
     obuf:i->o                 5.311          out3_t_i3 (tenthsout<7>)
    ----------------------------------------
    Total                      8.543ns (6.569ns logic, 1.974ns route)
                                       (76.9% logic, 23.1% route)

=========================================================================
CPU : 4.06 / 4.65 s | Elapsed : 4.00 / 5.00 s
 
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Total memory usage is 58500 kilobytes