stopwatch.syr

FPGA-CPLD_DesignTool(8-9-10)源代码

Release 5.1i - xst F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: stopwatch.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Low Level Synthesis
  6) Final Report
     6.1) Device utilization summary
     6.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : stopwatch.prj
Input Format                       : VHDL
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : stopwatch
Output Format                      : NGC
Target Device                      : xc2v40-5fg256

---- Source Options
Entity Name                        : stopwatch
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : lower
Top module area constraint         : 100
Top module allowed area overflow   : 5

---- Other Options
read_cores                         : YES
cross_clock_analysis               : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/cnt60.vhf in Library work.
Entity <ftce_mxilinx_cnt60> (Architecture <schematic>) compiled.
Entity <cb4ce_mxilinx_cnt60> (Architecture <schematic>) compiled.
Entity <cd4ce_mxilinx_cnt60> (Architecture <schematic>) compiled.
Entity <cnt60> (Architecture <schematic>) compiled.
Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd in Library work.
Entity <dcm1> (Architecture <struct>) compiled.
Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/decode.vhd in Library work.
Entity <decode> (Architecture <behavioral>) compiled.
Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/hex2led.vhd in Library work.
Entity <hex2led> (Architecture <behavioral>) compiled.
Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/outs3.vhf in Library work.
Entity <outs3> (Architecture <schematic>) compiled.
Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/STMACH_V.vhd in Library work.
Entity <stmach_v> (Architecture <behavior>) compiled.
Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/stopwatch.vhf in Library work.
Entity <stopwatch> (Architecture <schematic>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <stopwatch> (Architecture <schematic>).
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <xlxi_11> in unit <stopwatch>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <xlxi_10> in unit <stopwatch>.
    Set user-defined property "LOC =  A5" for instance <xlxi_10> in unit <stopwatch>.
WARNING:Xst:766 - J:/projects/ISE/ISEexamples/wtut_sc/stopwatch.vhf line 160: Generating a Black Box for component <tenths>.
Entity <stopwatch> analyzed. Unit <stopwatch> generated.

Analyzing Entity <cnt60> (Architecture <schematic>).
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/cnt60.vhf line 459: Unconnected output port 'ceo' of component 'cb4ce_mxilinx_cnt60'.
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/cnt60.vhf line 459: Unconnected output port 'tc' of component 'cb4ce_mxilinx_cnt60'.
    Set user-defined property "U_SET =  XLXI_3_5" for instance <xlxi_3> in unit <cnt60>.
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/cnt60.vhf line 464: Unconnected output port 'ceo' of component 'cd4ce_mxilinx_cnt60'.
    Set user-defined property "U_SET =  XLXI_2_4" for instance <xlxi_2> in unit <cnt60>.
Entity <cnt60> analyzed. Unit <cnt60> generated.

Analyzing Entity <dcm1> (Architecture <struct>).
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 110: Unconnected output port 'clk90' of component 'dcm'.
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 110: Unconnected output port 'clk180' of component 'dcm'.
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 110: Unconnected output port 'clk270' of component 'dcm'.
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 110: Unconnected output port 'clkdv' of component 'dcm'.
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 110: Unconnected output port 'clk2x' of component 'dcm'.
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 110: Unconnected output port 'clk2x180' of component 'dcm'.
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 110: Unconnected output port 'clkfx' of component 'dcm'.
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 110: Unconnected output port 'clkfx180' of component 'dcm'.
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 110: Unconnected output port 'status' of component 'dcm'.
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 110: Unconnected output port 'locked' of component 'dcm'.
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 110: Unconnected output port 'psdone' of component 'dcm'.
WARNING:Xst:766 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 110: Generating a Black Box for component <dcm>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <dcm_inst> in unit <dcm1>.
    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <dcm_inst> in unit <dcm1>.
    Set user-defined property "CLKFX_DIVIDE =  1" for instance <dcm_inst> in unit <dcm1>.
    Set user-defined property "CLKFX_MULTIPLY =  4" for instance <dcm_inst> in unit <dcm1>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  false" for instance <dcm_inst> in unit <dcm1>.
    Set user-defined property "CLKIN_PERIOD =  20.000000" for instance <dcm_inst> in unit <dcm1>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <dcm_inst> in unit <dcm1>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <dcm_inst> in unit <dcm1>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <dcm_inst> in unit <dcm1>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <dcm_inst> in unit <dcm1>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  true" for instance <dcm_inst> in unit <dcm1>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <dcm_inst> in unit <dcm1>.
    Set user-defined property "STARTUP_WAIT =  true" for instance <dcm_inst> in unit <dcm1>.
WARNING:Xst:766 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 137: Generating a Black Box for component <ibufg>.
WARNING:Xst:766 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 142: Generating a Black Box for component <bufg>.
Entity <dcm1> analyzed. Unit <dcm1> generated.

Analyzing Entity <decode> (Architecture <behavioral>).
Entity <decode> analyzed. Unit <decode> generated.

Analyzing Entity <hex2led> (Architecture <behavioral>).
Entity <hex2led> analyzed. Unit <hex2led> generated.

Analyzing Entity <outs3> (Architecture <schematic>).
    Set user-defined property "DRIVE =  12" for instance <i10> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <i10> in unit <outs3>.
    Set user-defined property "slew =  SLOW" for instance <i10> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <i9> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <i9> in unit <outs3>.
    Set user-defined property "slew =  SLOW" for instance <i9> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <i8> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <i8> in unit <outs3>.
    Set user-defined property "slew =  SLOW" for instance <i8> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <i7> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <i7> in unit <outs3>.
    Set user-defined property "slew =  SLOW" for instance <i7> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <i6> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <i6> in unit <outs3>.
    Set user-defined property "slew =  SLOW" for instance <i6> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <i5> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <i5> in unit <outs3>.
    Set user-defined property "slew =  SLOW" for instance <i5> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <i4> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <i4> in unit <outs3>.
    Set user-defined property "slew =  SLOW" for instance <i4> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <i3> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <i3> in unit <outs3>.
    Set user-defined property "slew =  SLOW" for instance <i3> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <i2> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <i2> in unit <outs3>.
    Set user-defined property "slew =  SLOW" for instance <i2> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <i1> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <i1> in unit <outs3>.
    Set user-defined property "slew =  SLOW" for instance <i1> in unit <outs3>.
Entity <outs3> analyzed. Unit <outs3> generated.

Analyzing Entity <stmach_v> (Architecture <behavior>).
Entity <stmach_v> analyzed. Unit <stmach_v> generated.

Analyzing Entity <cb4ce_mxilinx_cnt60> (Architecture <schematic>).
    Set user-defined property "U_SET =  I_Q0_0" for instance <i_q0> in unit <cb4ce_mxilinx_cnt60>.
    Set user-defined property "U_SET =  I_Q1_1" for instance <i_q1> in unit <cb4ce_mxilinx_cnt60>.
    Set user-defined property "U_SET =  I_Q2_2" for instance <i_q2> in unit <cb4ce_mxilinx_cnt60>.
    Set user-defined property "U_SET =  I_Q3_3" for instance <i_q3> in unit <cb4ce_mxilinx_cnt60>.
Entity <cb4ce_mxilinx_cnt60> analyzed. Unit <cb4ce_mxilinx_cnt60> generated.

Analyzing Entity <cd4ce_mxilinx_cnt60> (Architecture <schematic>).
    Set user-defined property "INIT =  0" for instance <i_q0> in unit <cd4ce_mxilinx_cnt60>.
    Set user-defined property "INIT =  0" for instance <i_q1> in unit <cd4ce_mxilinx_cnt60>.
    Set user-defined property "INIT =  0" for instance <i_q2> in unit <cd4ce_mxilinx_cnt60>.
    Set user-defined property "INIT =  0" for instance <i_q3> in unit <cd4ce_mxilinx_cnt60>.
Entity <cd4ce_mxilinx_cnt60> analyzed. Unit <cd4ce_mxilinx_cnt60> generated.

Analyzing Entity <ftce_mxilinx_cnt60> (Architecture <schematic>).
    Set user-defined property "INIT =  0" for instance <i_36_35> in unit <ftce_mxilinx_cnt60>.
    Set user-defined property "RLOC =  X0Y0" for instance <i_36_35> in unit <ftce_mxilinx_cnt60>.
Entity <ftce_mxilinx_cnt60> analyzed. Unit <ftce_mxilinx_cnt60> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <ftce_mxilinx_cnt60>.
    Related source file is J:/projects/ISE/ISEexamples/wtut_sc/cnt60.vhf.
Unit <ftce_mxilinx_cnt60> synthesized.


Synthesizing Unit <cd4ce_mxilinx_cnt60>.
    Related source file is J:/projects/ISE/ISEexamples/wtut_sc/cnt60.vhf.
Unit <cd4ce_mxilinx_cnt60> synthesized.


Synthesizing Unit <cb4ce_mxilinx_cnt60>.
    Related source file is J:/projects/ISE/ISEexamples/wtut_sc/cnt60.vhf.
Unit <cb4ce_mxilinx_cnt60> synthesized.


Synthesizing Unit <stmach_v>.
    Related source file is J:/projects/ISE/ISEexamples/wtut_sc/STMACH_V.vhd.
    Found finite state machine <FSM_0> for signal <sreg>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 11                                             |
    | Inputs             | 1                                              |
    | Outputs            | 2                                              |
    | Reset type         | asynchronous                                   |
    | Encoding           | automatic                                      |
    | State register     | d  flip-flops                                  |