stopwatch.cmd_log

FPGA-CPLD_DesignTool(8-9-10)源代码

sch2vhdl -family=virtex2 -flat -suppress -w stopwatch.sch stopwatch.vhf
xst -quiet -ifn __projnav/stopwatch.xst -ofn stopwatch.syr
ngdbuild -quiet -dd j:\projects\ise\iseexamples\wtut_sc/_ngo -i -insert_keep_hierarchy  -p xc2v40-fg256-5 stopwatch.ngc stopwatch.ngd
map -quiet -p xc2v40-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o stopwatch_map.ncd stopwatch.ngd stopwatch.pcf
par -w -ol 2 -t 1 stopwatch_map.ncd stopwatch.ncd stopwatch.pcf
trce -quiet -e 3 -l 3 -xml stopwatch stopwatch.ncd -o stopwatch.twr stopwatch.pcf
bitgen -f stopwatch.ut stopwatch.ncd
ngd2vhdl -quiet -rpw 100 -tpw 0 -ar Structure -xon false -w -log __projnav/ngd2vhdl.log stopwatch.ngd stopwatch_translate.vhd