wtut_sc.npl

FPGA-CPLD_DesignTool(8-9-10)源代码

JDF F
// Created by Project Navigator ver 1.0
PROJECT watch_sc
DESIGN wtut_sc Normal
DEVFAM virtex2
DEVFAMTIME 315558000
DEVICE xc2v40
DEVICETIME 315558000
DEVPKG fg256
DEVPKGTIME 315558000
DEVSPEED -5
DEVSPEEDTIME 315558000
FLOW XST VHDL
FLOWTIME 315558000
STIMULUS stopwatch_tb.vhd Normal
DOCUMENT readme.txt
DOCUMENT stmach_v.dia
MODULE outs3.sch
MODSTYLE outs3 Normal
MODULE DCM1.xaw
MODSTYLE DCM1 Normal
MODULE stopwatch.sch
MODSTYLE stopwatch Normal
MODULE hex2led.vhd
MODSTYLE hex2led Normal
MODULE STMACH_V.vhd
MODSTYLE stmach_v Normal
MODULE tenths.xco
MODSTYLE tenths Normal
MODULE CNT60.sch
MODSTYLE cnt60 Normal
MODULE decode.vhd
MODSTYLE decode Normal
[STATUS-ALL]
stopwatch.ngcFile=WARNINGS,1040292865
stopwatch.ngdFile=WARNINGS,1040292865
[STRATEGY-LIST]
Normal=True