tenths.coregen_log

FPGA-CPLD_DesignTool(8-9-10)源代码

# Xilinx CORE Generator 5.1i
# User = wcheng
# Initializing default project...
# Loading plug-ins...
# Initializing GUI...
SETPROJECT J:\projects\ISE\ISEexamples\wtut_sc
# lockprojectprops=false
# busformat=BusFormatAngleBracket
# designflow=Vhdl
# expandedprojectpath=J:\projects\ISE\ISEexamples\wtut_sc
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=Verilog VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# expandedprojectpath=J:\projects\ISE\ISEexamples\wtut_sc
# Set current Project to J:\projects\ISE\ISEexamples\wtut_sc
SELECT Binary_Counter Virtex2 Xilinx,_Inc. 5.0
CSET ce_override_for_load = false
CSET async_init_value = 1
CSET create_rpm = true
CSET clock_enable = true
CSET ce_overrides = sync_controls_override_ce
CSET load = false
CSET sync_init_value = 0
CSET load_sense = active_high
CSET operation = up
CSET threshold_1 = false
CSET threshold_0 = true
CSET count_style = count_by_constant
CSET restrict_count = true
CSET count_by_value = 1
CSET threshold_early = true
CSET asynchronous_settings = init
CSET threshold_1_value = MAX
CSET count_to_value = A
CSET threshold_0_value = A
CSET Component_Name = tenths
CSET threshold_options = registered
CSET set_clear_priority = clear_overrides_set
CSET output_width = 4
CSET synchronous_settings = none
GENERATE
# Preparing to elaborate core...
# Elaborating the module...
# Generating the core .EDN implementation netlist...
# Generating the .VHO/.VHD simulation support files...
# Generating the .VEO/.V simulation support files...
# Generating the .ASY symbol file...
# Generating ISE symbol file...
# Executing: J:\eda\Xilinx\bin\nt\coresupt.exe J:\projects\ISE\ISEexamples\wtut_sc\tenths.asy
# Execution Complete.  Return code: 0
# Successfully generated tenths (Binary Counter 5.0)
#  
END