stmach_v.vhi

FPGA-CPLD_DesignTool(8-9-10)源代码

-- VHDL Instantiation Created from source file stmach_v.vhd -- 18:14:07 12/19/2002
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT stmach_v
	PORT(
		clk : IN std_logic;
		reset : IN std_logic;
		strtstop : IN std_logic;          
		clkout : OUT std_logic;
		rst : OUT std_logic
		);
	END COMPONENT;

	Inst_stmach_v: stmach_v PORT MAP(
		clk => ,
		reset => ,
		strtstop => ,
		clkout => ,
		rst => 
	);