📄 stopwatch.mrp
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Release 5.1i - Map F.23Xilinx Mapping Report File for Design 'stopwatch'Design Information------------------Command Line : J:/eda/Xilinx/bin/nt/map.exe -quiet -p xc2v40-fg256-5 -cm area
-pr b -k 4 -c 100 -tx off -o stopwatch_map.ncd stopwatch.ngd stopwatch.pcf Target Device : x2v40Target Package : fg256Target Speed : -5Mapper Version : virtex2 -- $Revision: 1.4 $Mapped Date : Thu Dec 19 18:12:18 2002Design Summary-------------- Number of errors: 0 Number of warnings: 1 Number of Slices: 31 out of 256 12% Number of Slices containing unrelated logic: 0 out of 31 0% Number of Slice Flip Flops: 20 out of 512 3% Number of 4 input LUTs: 53 out of 512 10% Number of bonded IOBs: 27 out of 88 30% Number of GCLKs: 1 out of 16 6% Number of DCMs: 1 out of 4 25% Number of RPM macros: 1Total equivalent gate count for design: 7,502Additional JTAG gate count for IOBs: 1,296Peak Memory Usage: 54 MBTable of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
slice components. The resulting carry chain will have suboptimal timing. tenths_t/BU23 tenths_t/BU31Section 3 - Informational-------------------------INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0: bufg symbol "dcm1_t_clk0_bufg_inst" (output signal=clk_int)INFO:LIT:95 - All of the external outputs in this design are using slew rate
limited output drivers. The delay on speed critical outputs can be
dramatically reduced by designating them as fast outputs in the schematic.Section 4 - Removed Logic Summary--------------------------------- 4 block(s) removed 3 block(s) optimized away 3 signal(s) removedSection 5 - Removed Logic-------------------------The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections. If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented. This
indentation will be repeated as a chain of related logic is removed.To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).The signal "cnt60_t_xlxi_2/ceo" is sourceless and has been removed.The signal "cnt60_t_xlxi_3/ceo" is sourceless and has been removed.The signal "cnt60_t_xlxi_3/tc" is sourceless and has been removed. Sourceless block "cnt60_t_xlxi_3/i_36_67" (AND) removed.Unused block "cnt60_t_xlxi_2/i_36_99" (AND) removed.Unused block "cnt60_t_xlxi_3/i_36_31" (AND) removed.Unused block "tenths_t/VCC" (ONE) removed.Optimized Block(s):TYPE BLOCKvcc cnt60_t_xlxi_3/i_36_58GND tenths_t/GNDGND xst_gndTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+------------------------------------------------------------------------------------------------------------------------+| clk | IOB | INPUT | LVTTL | | | | | || onesout<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || onesout<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || onesout<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || onesout<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || onesout<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || onesout<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || onesout<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || reset | IOB | INPUT | LVTTL | | | | | || starstop | IOB | INPUT | LVTTL | | | | | || tensout<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || tensout<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || tensout<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || tensout<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || tensout<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || tensout<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || tensout<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || tenthsout<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || tenthsout<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || tenthsout<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || tenthsout<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || tenthsout<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || tenthsout<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || tenthsout<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || tenthsout<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || tenthsout<8> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || tenthsout<9> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------XLXI_3_5 XLXI_2_4 tenths_t/hset I_Q3_3 I_Q2_2 I_Q1_1 I_Q0_0 Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.⌨️ 快捷键说明
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