stopwatch.twr

FPGA-CPLD_DesignTool(8-9-10)源代码

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Release 5.1i - Trace F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

J:/eda/Xilinx/bin/nt/trce.exe -quiet -e 3 -l 3 -xml stopwatch stopwatch.ncd -o
stopwatch.twr stopwatch.pcf

Design file:              stopwatch.ncd
Physical constraint file: stopwatch.pcf
Device,speed:             xc2v40,-5 (ADVANCED 1.110 2002-07-03, STEPPING level 1)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
---------------+------------+------------+
               |  Setup to  |  Hold to   |
Source Pad     | clk (edge) | clk (edge) |
---------------+------------+------------+
starstop       |    3.311(R)|   -2.534(R)|
---------------+------------+------------+

Clock clk to Pad
---------------+------------+
               | clk (edge) |
Destination Pad|   to PAD   |
---------------+------------+
onesout<0>     |    7.241(R)|
onesout<1>     |    7.534(R)|
onesout<2>     |    7.941(R)|
onesout<3>     |    7.204(R)|
onesout<4>     |    7.986(R)|
onesout<5>     |    7.502(R)|
onesout<6>     |    7.503(R)|
tensout<0>     |    7.830(R)|
tensout<1>     |    7.862(R)|
tensout<2>     |    7.716(R)|
tensout<3>     |    7.177(R)|
tensout<4>     |    8.000(R)|
tensout<5>     |    7.761(R)|
tensout<6>     |    7.940(R)|
tenthsout<0>   |    7.814(R)|
tenthsout<1>   |    8.332(R)|
tenthsout<2>   |    7.877(R)|
tenthsout<3>   |    7.940(R)|
tenthsout<4>   |    8.153(R)|
tenthsout<5>   |    8.545(R)|
tenthsout<6>   |    8.326(R)|
tenthsout<7>   |    8.116(R)|
tenthsout<8>   |    8.608(R)|
tenthsout<9>   |    8.091(R)|
---------------+------------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    4.195|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Thu Dec 19 18:12:25 2002
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