stopwatch.vhf

FPGA-CPLD_DesignTool(8-9-10)源代码

-- Vhdl model created from schematic stopwatch.sch - Thu Dec 19 18:12:07 2002

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-- synopsys translate_off
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
-- synopsys translate_on

ENTITY stopwatch IS
   PORT ( clk	:	IN	STD_LOGIC; 
          reset	:	IN	STD_LOGIC; 
          starstop	:	IN	STD_LOGIC; 
          onesout	:	OUT	STD_LOGIC_VECTOR (6 DOWNTO 0); 
          tensout	:	OUT	STD_LOGIC_VECTOR (6 DOWNTO 0); 
          tenthsout	:	OUT	STD_LOGIC_VECTOR (9 DOWNTO 0));

end stopwatch;

ARCHITECTURE SCHEMATIC OF stopwatch IS
   SIGNAL XLXN_105	:	STD_LOGIC;
   SIGNAL XLXN_2	:	STD_LOGIC;
   SIGNAL XLXN_3	:	STD_LOGIC;
   SIGNAL XLXN_35	:	STD_LOGIC_VECTOR (3 DOWNTO 0);
   SIGNAL XLXN_36	:	STD_LOGIC_VECTOR (9 DOWNTO 0);
   SIGNAL XLXN_5	:	STD_LOGIC;
   SIGNAL XLXN_95	:	STD_LOGIC;
   SIGNAL XLXN_96	:	STD_LOGIC_VECTOR (3 DOWNTO 0);
   SIGNAL XLXN_97	:	STD_LOGIC_VECTOR (3 DOWNTO 0);
   SIGNAL clk_int	:	STD_LOGIC;
   SIGNAL clken_int	:	STD_LOGIC;
   SIGNAL rst_int	:	STD_LOGIC;

   ATTRIBUTE BOX_TYPE : STRING;
   ATTRIBUTE IOSTANDARD : STRING ;
   ATTRIBUTE IOSTANDARD OF XLXI_11 : LABEL IS "LVTTL";
   ATTRIBUTE LOC : STRING ;
   ATTRIBUTE IOSTANDARD OF XLXI_10 : LABEL IS "LVTTL";
   ATTRIBUTE LOC OF XLXI_10 : LABEL IS "A5";

   COMPONENT AND2
      PORT ( I0	:	IN	STD_LOGIC; 
             I1	:	IN	STD_LOGIC; 
             O	:	OUT	STD_LOGIC);
   END COMPONENT;

   ATTRIBUTE BOX_TYPE OF AND2 : COMPONENT IS "BLACK_BOX";
   COMPONENT cnt60
      PORT ( ce	:	IN	STD_LOGIC; 
             clk	:	IN	STD_LOGIC; 
             clr	:	IN	STD_LOGIC; 
             lsbsec	:	OUT	STD_LOGIC_VECTOR (3 DOWNTO 0); 
             msbsec	:	OUT	STD_LOGIC_VECTOR (3 DOWNTO 0));
   END COMPONENT;

   COMPONENT dcm1
      PORT ( CLKIN_IN	:	IN	STD_LOGIC; 
             CLK0_OUT	:	OUT	STD_LOGIC);
   END COMPONENT;

   COMPONENT decode
      PORT ( binary	:	IN	STD_LOGIC_VECTOR (3 DOWNTO 0); 
             one_hot	:	OUT	STD_LOGIC_VECTOR (9 DOWNTO 0));
   END COMPONENT;

   COMPONENT hex2led
      PORT ( hex	:	IN	STD_LOGIC_VECTOR (3 DOWNTO 0); 
             led	:	OUT	STD_LOGIC_VECTOR (6 DOWNTO 0));
   END COMPONENT;

   COMPONENT IBUF
      PORT ( I	:	IN	STD_LOGIC; 
             O	:	OUT	STD_LOGIC);
   END COMPONENT;

   ATTRIBUTE BOX_TYPE OF IBUF : COMPONENT IS "BLACK_BOX";
   COMPONENT INV
      PORT ( I	:	IN	STD_LOGIC; 
             O	:	OUT	STD_LOGIC);
   END COMPONENT;

   ATTRIBUTE BOX_TYPE OF INV : COMPONENT IS "BLACK_BOX";
   COMPONENT outs3
      PORT ( inputs	:	IN	STD_LOGIC_VECTOR (9 DOWNTO 0); 
             outs	:	OUT	STD_LOGIC_VECTOR (9 DOWNTO 0));
   END COMPONENT;

   COMPONENT stmach_v
      PORT ( clk	:	IN	STD_LOGIC; 
             reset	:	IN	STD_LOGIC; 
             strtstop	:	IN	STD_LOGIC; 
             clkout	:	OUT	STD_LOGIC; 
             rst	:	OUT	STD_LOGIC);
   END COMPONENT;

   COMPONENT tenths
      PORT ( CE	:	IN	STD_LOGIC; 
             CLK	:	IN	STD_LOGIC; 
             Q_THRESH0	:	OUT	STD_LOGIC; 
             Q	:	OUT	STD_LOGIC_VECTOR (3 DOWNTO 0); 
             AINIT	:	IN	STD_LOGIC);
   END COMPONENT;

BEGIN

   XLXI_22 : AND2
      PORT MAP (I0=>clken_int, I1=>XLXN_105, O=>XLXN_95);

   cnt60_t : cnt60
      PORT MAP (ce=>XLXN_95, clk=>clk_int, clr=>rst_int, lsbsec(3)=>XLXN_96(3),
      lsbsec(2)=>XLXN_96(2), lsbsec(1)=>XLXN_96(1), lsbsec(0)=>XLXN_96(0),
      msbsec(3)=>XLXN_97(3), msbsec(2)=>XLXN_97(2), msbsec(1)=>XLXN_97(1),
      msbsec(0)=>XLXN_97(0));

   dcm1_t : dcm1
      PORT MAP (CLKIN_IN=>clk, CLK0_OUT=>clk_int);

   decode_t : decode
      PORT MAP (binary(3)=>XLXN_35(3), binary(2)=>XLXN_35(2),
      binary(1)=>XLXN_35(1), binary(0)=>XLXN_35(0), one_hot(9)=>XLXN_36(9),
      one_hot(8)=>XLXN_36(8), one_hot(7)=>XLXN_36(7), one_hot(6)=>XLXN_36(6),
      one_hot(5)=>XLXN_36(5), one_hot(4)=>XLXN_36(4), one_hot(3)=>XLXN_36(3),
      one_hot(2)=>XLXN_36(2), one_hot(1)=>XLXN_36(1), one_hot(0)=>XLXN_36(0));

   hex2led2 : hex2led
      PORT MAP (hex(3)=>XLXN_97(3), hex(2)=>XLXN_97(2), hex(1)=>XLXN_97(1),
      hex(0)=>XLXN_97(0), led(6)=>tensout(6), led(5)=>tensout(5),
      led(4)=>tensout(4), led(3)=>tensout(3), led(2)=>tensout(2),
      led(1)=>tensout(1), led(0)=>tensout(0));

   hex2led1 : hex2led
      PORT MAP (hex(3)=>XLXN_96(3), hex(2)=>XLXN_96(2), hex(1)=>XLXN_96(1),
      hex(0)=>XLXN_96(0), led(6)=>onesout(6), led(5)=>onesout(5),
      led(4)=>onesout(4), led(3)=>onesout(3), led(2)=>onesout(2),
      led(1)=>onesout(1), led(0)=>onesout(0));

   XLXI_11 : IBUF
      PORT MAP (I=>starstop, O=>XLXN_5);

   XLXI_10 : IBUF
      PORT MAP (I=>reset, O=>XLXN_2);

   XLXI_9 : INV
      PORT MAP (I=>XLXN_2, O=>XLXN_3);

   out3_t : outs3
      PORT MAP (inputs(9)=>XLXN_36(9), inputs(8)=>XLXN_36(8),
      inputs(7)=>XLXN_36(7), inputs(6)=>XLXN_36(6), inputs(5)=>XLXN_36(5),
      inputs(4)=>XLXN_36(4), inputs(3)=>XLXN_36(3), inputs(2)=>XLXN_36(2),
      inputs(1)=>XLXN_36(1), inputs(0)=>XLXN_36(0), outs(9)=>tenthsout(9),
      outs(8)=>tenthsout(8), outs(7)=>tenthsout(7), outs(6)=>tenthsout(6),
      outs(5)=>tenthsout(5), outs(4)=>tenthsout(4), outs(3)=>tenthsout(3),
      outs(2)=>tenthsout(2), outs(1)=>tenthsout(1), outs(0)=>tenthsout(0));

   stmach_t : stmach_v
      PORT MAP (clk=>clk_int, reset=>XLXN_3, strtstop=>XLXN_5,
      clkout=>clken_int, rst=>rst_int);

   tenths_t : tenths
      PORT MAP (CE=>clken_int, CLK=>clk_int, Q_THRESH0=>XLXN_105,
      Q(3)=>XLXN_35(3), Q(2)=>XLXN_35(2), Q(1)=>XLXN_35(1), Q(0)=>XLXN_35(0),
      AINIT=>rst_int);

END SCHEMATIC;