cnt60.sym

FPGA-CPLD_DesignTool(8-9-10)源代码

VERSION 5
BEGIN SYMBOL 
SYMBOLTYPE BLOCK
TIMESTAMP 2002 11 12 0 50 21
SYMPIN 0 -160 Input "ce"
SYMPIN 0 -96 Input "clk"
SYMPIN 0 -32 Input "clr"
SYMPIN 416 -160 Output "lsbsec(3:0)"
SYMPIN 416 -32 Output "msbsec(3:0)"
RECTANGLE N 64 -192 352 0 
BEGIN DISPLAY 208 -200 ATTR "SymbolName"
    ALIGNMENT BCENTER
    FONT 56 "Arial"
END DISPLAY
LINE N 64 -160 0 -160 
BEGIN DISPLAY 72 -160 PIN "ce" ATTR "PinName"
    FONT 24 "Arial"
END DISPLAY
LINE N 64 -96 0 -96 
BEGIN DISPLAY 72 -96 PIN "clk" ATTR "PinName"
    FONT 24 "Arial"
END DISPLAY
LINE N 64 -32 0 -32 
BEGIN DISPLAY 72 -32 PIN "clr" ATTR "PinName"
    FONT 24 "Arial"
END DISPLAY
LINE N 352 -160 416 -160 
BEGIN DISPLAY 344 -160 PIN "lsbsec(3:0)" ATTR "PinName"
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
RECTANGLE N 352 -172 416 -148 
LINE N 352 -32 416 -32 
BEGIN DISPLAY 344 -32 PIN "msbsec(3:0)" ATTR "PinName"
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
RECTANGLE N 352 -44 416 -20 
END SYMBOL