stopwatch.schbak

FPGA-CPLD_DesignTool(8-9-10)源代码

VERSION 5
BEGIN SCHEMATIC
    BEGIN ATTR DeviceFamilyName Virtex
        DELETE all:0
        EDITNAME all:0
        EDITTRAIT all:0
    End ATTR
    BEGIN NETLIST
        SIGNAL tenthsout(9:0)
        SIGNAL onesout(6:0)
        SIGNAL tensout(6:0)
        PORT Output tenthsout(9:0)
        PORT Output onesout(6:0)
        PORT Output tensout(6:0)
    END NETLIST
    BEGIN SHEET 1 5440 3520
        BEGIN BRANCH tenthsout(9:0)
            WIRE 1856 832 1952 832
            WIRE 1952 832 1984 832
            WIRE 1984 832 2000 832
        END BRANCH
        IOMARKER 2000 832 tenthsout(9:0)
        BEGIN BRANCH onesout(6:0)
            WIRE 1792 1264 1856 1264
            WIRE 1856 1264 1968 1264
            WIRE 1968 1264 1984 1264
        END BRANCH
        IOMARKER 1984 1264 onesout(6:0)
        BEGIN BRANCH tensout(6:0)
            WIRE 1792 1488 1856 1488
            WIRE 1856 1488 1968 1488
            WIRE 1968 1488 1984 1488
        END BRANCH
        IOMARKER 1984 1488 tensout(6:0)
    END SHEET
END SCHEMATIC