outs3.vhf

FPGA-CPLD_DesignTool(8-9-10)源代码

-- Vhdl model created from schematic outs3.sch - Thu Dec 19 18:12:09 2002

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-- synopsys translate_off
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
-- synopsys translate_on

ENTITY outs3 IS
   PORT ( inputs	:	IN	STD_LOGIC_VECTOR (9 DOWNTO 0); 
          outs	:	OUT	STD_LOGIC_VECTOR (9 DOWNTO 0));

end outs3;

ARCHITECTURE SCHEMATIC OF outs3 IS
   SIGNAL XLXN_12	:	STD_LOGIC;
   SIGNAL XLXN_13	:	STD_LOGIC;
   SIGNAL XLXN_14	:	STD_LOGIC;
   SIGNAL XLXN_15	:	STD_LOGIC;
   SIGNAL XLXN_16	:	STD_LOGIC;
   SIGNAL XLXN_17	:	STD_LOGIC;
   SIGNAL XLXN_18	:	STD_LOGIC;
   SIGNAL XLXN_19	:	STD_LOGIC;
   SIGNAL XLXN_20	:	STD_LOGIC;
   SIGNAL XLXN_21	:	STD_LOGIC;

   ATTRIBUTE BOX_TYPE : STRING;
   ATTRIBUTE DRIVE : STRING ;
   ATTRIBUTE IOSTANDARD : STRING ;
   ATTRIBUTE SLEW : STRING ;
   ATTRIBUTE DRIVE OF I10 : LABEL IS "12";
   ATTRIBUTE IOSTANDARD OF I10 : LABEL IS "LVTTL";
   ATTRIBUTE SLEW OF I10 : LABEL IS "SLOW";
   ATTRIBUTE DRIVE OF I9 : LABEL IS "12";
   ATTRIBUTE IOSTANDARD OF I9 : LABEL IS "LVTTL";
   ATTRIBUTE SLEW OF I9 : LABEL IS "SLOW";
   ATTRIBUTE DRIVE OF I8 : LABEL IS "12";
   ATTRIBUTE IOSTANDARD OF I8 : LABEL IS "LVTTL";
   ATTRIBUTE SLEW OF I8 : LABEL IS "SLOW";
   ATTRIBUTE DRIVE OF I7 : LABEL IS "12";
   ATTRIBUTE IOSTANDARD OF I7 : LABEL IS "LVTTL";
   ATTRIBUTE SLEW OF I7 : LABEL IS "SLOW";
   ATTRIBUTE DRIVE OF I6 : LABEL IS "12";
   ATTRIBUTE IOSTANDARD OF I6 : LABEL IS "LVTTL";
   ATTRIBUTE SLEW OF I6 : LABEL IS "SLOW";
   ATTRIBUTE DRIVE OF I5 : LABEL IS "12";
   ATTRIBUTE IOSTANDARD OF I5 : LABEL IS "LVTTL";
   ATTRIBUTE SLEW OF I5 : LABEL IS "SLOW";
   ATTRIBUTE DRIVE OF I4 : LABEL IS "12";
   ATTRIBUTE IOSTANDARD OF I4 : LABEL IS "LVTTL";
   ATTRIBUTE SLEW OF I4 : LABEL IS "SLOW";
   ATTRIBUTE DRIVE OF I3 : LABEL IS "12";
   ATTRIBUTE IOSTANDARD OF I3 : LABEL IS "LVTTL";
   ATTRIBUTE SLEW OF I3 : LABEL IS "SLOW";
   ATTRIBUTE DRIVE OF I2 : LABEL IS "12";
   ATTRIBUTE IOSTANDARD OF I2 : LABEL IS "LVTTL";
   ATTRIBUTE SLEW OF I2 : LABEL IS "SLOW";
   ATTRIBUTE DRIVE OF I1 : LABEL IS "12";
   ATTRIBUTE IOSTANDARD OF I1 : LABEL IS "LVTTL";
   ATTRIBUTE SLEW OF I1 : LABEL IS "SLOW";

   COMPONENT INV
      PORT ( I	:	IN	STD_LOGIC; 
             O	:	OUT	STD_LOGIC);
   END COMPONENT;

   ATTRIBUTE BOX_TYPE OF INV : COMPONENT IS "BLACK_BOX";
   COMPONENT OBUF
      PORT ( I	:	IN	STD_LOGIC; 
             O	:	OUT	STD_LOGIC);
   END COMPONENT;

   ATTRIBUTE BOX_TYPE OF OBUF : COMPONENT IS "BLACK_BOX";
BEGIN

   I11 : INV
      PORT MAP (I=>inputs(0), O=>XLXN_21);

   I12 : INV
      PORT MAP (I=>inputs(9), O=>XLXN_12);

   I13 : INV
      PORT MAP (I=>inputs(8), O=>XLXN_13);

   I14 : INV
      PORT MAP (I=>inputs(7), O=>XLXN_14);

   I15 : INV
      PORT MAP (I=>inputs(6), O=>XLXN_15);

   I16 : INV
      PORT MAP (I=>inputs(5), O=>XLXN_16);

   I17 : INV
      PORT MAP (I=>inputs(4), O=>XLXN_17);

   I18 : INV
      PORT MAP (I=>inputs(3), O=>XLXN_18);

   I19 : INV
      PORT MAP (I=>inputs(2), O=>XLXN_19);

   I20 : INV
      PORT MAP (I=>inputs(1), O=>XLXN_20);

   I10 : OBUF
      PORT MAP (I=>XLXN_21, O=>outs(0));

   I9 : OBUF
      PORT MAP (I=>XLXN_20, O=>outs(1));

   I8 : OBUF
      PORT MAP (I=>XLXN_19, O=>outs(2));

   I7 : OBUF
      PORT MAP (I=>XLXN_18, O=>outs(3));

   I6 : OBUF
      PORT MAP (I=>XLXN_17, O=>outs(4));

   I5 : OBUF
      PORT MAP (I=>XLXN_16, O=>outs(5));

   I4 : OBUF
      PORT MAP (I=>XLXN_15, O=>outs(6));

   I3 : OBUF
      PORT MAP (I=>XLXN_14, O=>outs(7));

   I2 : OBUF
      PORT MAP (I=>XLXN_13, O=>outs(8));

   I1 : OBUF
      PORT MAP (I=>XLXN_12, O=>outs(9));

END SCHEMATIC;