stopwatch.sym

FPGA-CPLD_DesignTool(8-9-10)源代码

VERSION 5
BEGIN SYMBOL 
SYMBOLTYPE BLOCK
TIMESTAMP 2002 11 12 2 50 25
SYMPIN 0 -160 Input "clk"
SYMPIN 0 -96 Input "reset"
SYMPIN 0 -32 Input "starstop"
SYMPIN 384 -160 Output "tenthsout(9:0)"
SYMPIN 384 -96 Output "onesout(6:0)"
SYMPIN 384 -32 Output "tensout(6:0)"
BEGIN DISPLAY 192 -200 ATTR "SymbolName"
    ALIGNMENT BCENTER
    FONT 56 "Arial"
END DISPLAY
BEGIN DISPLAY 72 -160 PIN "clk" ATTR "PinName"
    FONT 24 "Arial"
END DISPLAY
BEGIN DISPLAY 72 -96 PIN "reset" ATTR "PinName"
    FONT 24 "Arial"
END DISPLAY
BEGIN DISPLAY 72 -32 PIN "starstop" ATTR "PinName"
    FONT 24 "Arial"
END DISPLAY
BEGIN DISPLAY 312 -160 PIN "tenthsout(9:0)" ATTR "PinName"
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
BEGIN DISPLAY 312 -96 PIN "onesout(6:0)" ATTR "PinName"
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
BEGIN DISPLAY 312 -32 PIN "tensout(6:0)" ATTR "PinName"
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
RECTANGLE N 64 -192 320 0 
LINE N 64 -160 0 -160 
LINE N 64 -96 0 -96 
LINE N 64 -32 0 -32 
LINE N 320 -160 384 -160 
RECTANGLE N 320 -172 384 -148 
LINE N 320 -96 384 -96 
RECTANGLE N 320 -108 384 -84 
LINE N 320 -32 384 -32 
RECTANGLE N 320 -44 384 -20 
END SYMBOL