hex2led.sym

FPGA-CPLD_DesignTool(8-9-10)源代码

VERSION 5
BEGIN SYMBOL 
SYMBOLTYPE BLOCK
TIMESTAMP 2002 12 19 10 13 51
SYMPIN 0 -32 Input "hex(3:0)"
SYMPIN 400 -32 Output "led(6:0)"
BEGIN DISPLAY 200 -72 ATTR "SymbolName"
    ALIGNMENT BCENTER
    FONT 56 "Arial"
END DISPLAY
BEGIN DISPLAY 72 -32 PIN "hex(3:0)" ATTR "PinName"
    FONT 24 "Arial"
END DISPLAY
BEGIN DISPLAY 328 -32 PIN "led(6:0)" ATTR "PinName"
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
RECTANGLE N 64 -64 336 0 
LINE N 64 -32 0 -32 
RECTANGLE N 0 -44 64 -20 
LINE N 336 -32 400 -32 
RECTANGLE N 336 -44 400 -20 
END SYMBOL