stopwatch_tb.vhd

FPGA-CPLD_DesignTool(8-9-10)源代码

LIBRARY  IEEE;
USE IEEE.std_logic_1164.all;

LIBRARY ieee;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE testbench_arch OF testbench IS

COMPONENT stopwatch
	PORT (
		CLK : in  STD_LOGIC;
		RESET : in  STD_LOGIC;
		STRTSTOP : in  STD_LOGIC;
		TENTHSOUT : out  STD_LOGIC_VECTOR (9 DOWNTO 0);
		ONESOUT : out  STD_LOGIC_VECTOR (6 DOWNTO 0);
		TENSOUT : out  STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END COMPONENT;

SIGNAL CLK : STD_LOGIC;
SIGNAL RESET : STD_LOGIC;
SIGNAL STRTSTOP : STD_LOGIC;
SIGNAL TENTHSOUT : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL ONESOUT : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL TENSOUT : STD_LOGIC_VECTOR (6 DOWNTO 0);
constant ClockPeriod : Time := 10 ns;


BEGIN



UUT : stopwatch
	PORT MAP (
		CLK => CLK,
		RESET => RESET,
		STRTSTOP => STRTSTOP,
		TENTHSOUT => TENTHSOUT,
		ONESOUT => ONESOUT,
		TENSOUT => TENSOUT
	);

generateclock: process
begin
clk <= '1';
loop
wait for (ClockPeriod / 2);
CLK <= not CLK;
end loop;  
end process;

stimulus: process
begin
reset <= '1';
strtstop <= '1';
  wait for 50 ns;
reset <= '0';
  wait for 500 ns;
strtstop <= '0';
  wait for 5000 ns;
strtstop <= '1';
  wait for 4000 ns;
strtstop <= '0';
  wait for 2000 ns;
strtstop <= '1';

end process stimulus;

end testbench_arch;


library XilinxCoreLib;

CONFIGURATION stopwatch_cfg OF testbench IS
	FOR testbench_arch
		FOR ALL : stopwatch use configuration work.cfg_tenths;
		END FOR;
	END FOR;
END stopwatch_cfg;