dcm1.sym

来自「FPGA-CPLD_DesignTool(8-9-10)源代码」· SYM 代码 · 共 22 行

VERSION 5
BEGIN SYMBOL 
SYMBOLTYPE BLOCK
TIMESTAMP 2004 10 12 14 48 37
SYMPIN 0 -32 Input CLKIN_IN
SYMPIN 384 -32 Output CLK0_OUT
RECTANGLE N 64 -64 320 0 
BEGIN DISPLAY 192 -72 ATTR SymbolName
    ALIGNMENT BCENTER
    FONT 56 "Arial"
END DISPLAY
LINE N 64 -32 0 -32 
BEGIN DISPLAY 72 -32 PIN CLKIN_IN ATTR PinName
    FONT 24 "Arial"
END DISPLAY
LINE N 320 -32 384 -32 
BEGIN DISPLAY 312 -32 PIN CLK0_OUT ATTR PinName
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
END SYMBOL