cnt60.vf

FPGA-CPLD_DesignTool(8-9-10)源代码

// Verilog model created from C:\eda\Xilinx\virtex2\data\drawing\ftce.sch - Tue Oct 12 23:20:43 2004

`timescale 1ns / 1ps

module FTCE_MXILINX_cnt60(C, CE, CLR, T, Q);

    input C;
    input CE;
    input CLR;
    input T;
   output Q;
   
   wire TQ;
   
   XOR2 I_36_32 (.I0(T), .I1(Q), .O(TQ));
   FDCE I_36_35 (.C(C), .CE(CE), .CLR(CLR), .D(TQ), .Q(Q));
   // synthesis attribute RLOC of I_36_35 is "X0Y0"
   // synthesis attribute INIT of I_36_35 is "0"
   // synopsys translate_off
   defparam I_36_35.INIT = 1'b0;
   // synopsys translate_on
endmodule
// Verilog model created from C:\eda\Xilinx\virtex2\data\drawing\cb4ce.sch - Tue Oct 12 23:20:43 2004

`timescale 1ns / 1ps

module CB4CE_MXILINX_cnt60(C, CE, CLR, CEO, Q0, Q1, Q2, Q3, TC);

    input C;
    input CE;
    input CLR;
   output CEO;
   output Q0;
   output Q1;
   output Q2;
   output Q3;
   output TC;
   
   wire T2;
   wire T3;
   wire XLXN_1;
   
   FTCE_MXILINX_cnt60 I_Q0 (.C(C), .CE(CE), .CLR(CLR), .T(XLXN_1), .Q(Q0));
   // synthesis attribute HU_SET of I_Q0 is "I_Q0_0"
   FTCE_MXILINX_cnt60 I_Q1 (.C(C), .CE(CE), .CLR(CLR), .T(Q0), .Q(Q1));
   // synthesis attribute HU_SET of I_Q1 is "I_Q1_1"
   FTCE_MXILINX_cnt60 I_Q2 (.C(C), .CE(CE), .CLR(CLR), .T(T2), .Q(Q2));
   // synthesis attribute HU_SET of I_Q2 is "I_Q2_2"
   FTCE_MXILINX_cnt60 I_Q3 (.C(C), .CE(CE), .CLR(CLR), .T(T3), .Q(Q3));
   // synthesis attribute HU_SET of I_Q3 is "I_Q3_3"
   AND4 I_36_31 (.I0(Q3), .I1(Q2), .I2(Q1), .I3(Q0), .O(TC));
   AND3 I_36_32 (.I0(Q2), .I1(Q1), .I2(Q0), .O(T3));
   AND2 I_36_33 (.I0(Q1), .I1(Q0), .O(T2));
   VCC I_36_58 (.P(XLXN_1));
   AND2 I_36_67 (.I0(CE), .I1(TC), .O(CEO));
endmodule
// Verilog model created from C:\eda\Xilinx\virtex2\data\drawing\cd4ce.sch - Tue Oct 12 23:20:43 2004

`timescale 1ns / 1ps

module CD4CE_MXILINX_cnt60(C, CE, CLR, CEO, Q0, Q1, Q2, Q3, TC);

    input C;
    input CE;
    input CLR;
   output CEO;
   output Q0;
   output Q1;
   output Q2;
   output Q3;
   output TC;
   
   wire AO3A;
   wire AX1;
   wire AX2;
   wire A03B;
   wire D0;
   wire D1;
   wire D2;
   wire D3;
   wire OX3;
   
   FDCE I_Q0 (.C(C), .CE(CE), .CLR(CLR), .D(D0), .Q(Q0));
   // synthesis attribute INIT of I_Q0 is "0"
   // synopsys translate_off
   defparam I_Q0.INIT = 1'b0;
   // synopsys translate_on
   FDCE I_Q1 (.C(C), .CE(CE), .CLR(CLR), .D(D1), .Q(Q1));
   // synthesis attribute INIT of I_Q1 is "0"
   // synopsys translate_off
   defparam I_Q1.INIT = 1'b0;
   // synopsys translate_on
   FDCE I_Q2 (.C(C), .CE(CE), .CLR(CLR), .D(D2), .Q(Q2));
   // synthesis attribute INIT of I_Q2 is "0"
   // synopsys translate_off
   defparam I_Q2.INIT = 1'b0;
   // synopsys translate_on
   FDCE I_Q3 (.C(C), .CE(CE), .CLR(CLR), .D(D3), .Q(Q3));
   // synthesis attribute INIT of I_Q3 is "0"
   // synopsys translate_off
   defparam I_Q3.INIT = 1'b0;
   // synopsys translate_on
   AND3 I_36_70 (.I0(Q2), .I1(Q0), .I2(Q1), .O(A03B));
   XOR2 I_36_73 (.I0(Q3), .I1(OX3), .O(D3));
   OR2 I_36_75 (.I0(AO3A), .I1(A03B), .O(OX3));
   AND2 I_36_77 (.I0(Q0), .I1(Q1), .O(AX2));
   XOR2 I_36_78 (.I0(Q2), .I1(AX2), .O(D2));
   AND2B1 I_36_81 (.I0(Q3), .I1(Q0), .O(AX1));
   INV I_36_83 (.I(Q0), .O(D0));
   XOR2 I_36_86 (.I0(Q1), .I1(AX1), .O(D1));
   AND2 I_36_88 (.I0(Q3), .I1(Q0), .O(AO3A));
   AND2 I_36_99 (.I0(CE), .I1(TC), .O(CEO));
   AND4B2 I_36_105 (.I0(Q2), .I1(Q1), .I2(Q0), .I3(Q3), .O(TC));
endmodule
// Verilog model created from cnt60.sch - Tue Oct 12 23:20:43 2004

`timescale 1ns / 1ps

module cnt60(ce, clk, clr, lsbsec, msbsec);

    input ce;
    input clk;
    input clr;
   output [3:0] lsbsec;
   output [3:0] msbsec;
   
   wire XLXN_8;
   wire XLXN_9;
   wire XLXN_15;
   wire XLXN_16;
   wire XLXN_24;
   wire XLXN_26;
   wire XLXN_27;
   
   AND2 XLXI_1 (.I0(XLXN_24), .I1(XLXN_27), .O(XLXN_26));
   CD4CE_MXILINX_cnt60 XLXI_2 (.C(clk), .CE(ce), .CLR(clr), .CEO(),
         .Q0(lsbsec[0]), .Q1(lsbsec[1]), .Q2(lsbsec[2]), .Q3(lsbsec[3]),
         .TC(XLXN_8));
   // synthesis attribute HU_SET of XLXI_2 is "XLXI_2_4"
   CB4CE_MXILINX_cnt60 XLXI_3 (.C(clk), .CE(XLXN_27), .CLR(XLXN_9), .CEO(),
         .Q0(msbsec[0]), .Q1(msbsec[1]), .Q2(msbsec[2]), .Q3(msbsec[3]), .TC());
   // synthesis attribute HU_SET of XLXI_3 is "XLXI_3_5"
   OR2 XLXI_4 (.I0(XLXN_26), .I1(clr), .O(XLXN_9));
   INV XLXI_5 (.I(msbsec[1]), .O(XLXN_16));
   AND4 XLXI_6 (.I0(XLXN_15), .I1(msbsec[2]), .I2(XLXN_16), .I3(msbsec[0]),
         .O(XLXN_24));
   AND2 XLXI_7 (.I0(ce), .I1(XLXN_8), .O(XLXN_27));
   INV XLXI_8 (.I(msbsec[3]), .O(XLXN_15));
endmodule