stopwatch.vf

FPGA-CPLD_DesignTool(8-9-10)源代码

// Verilog model created from stopwatch.sch - Tue Oct 12 23:20:43 2004

`timescale 1ns / 1ps

module stopwatch(clk, reset, starstop, onesout, tensout, tenthsout);

    input clk;
    input reset;
    input starstop;
   output [6:0] onesout;
   output [6:0] tensout;
   output [9:0] tenthsout;
   
   wire clken_int;
   wire clk_int;
   wire rst_int;
   wire XLXN_2;
   wire XLXN_3;
   wire XLXN_5;
   wire [3:0] XLXN_35;
   wire [9:0] XLXN_36;
   wire XLXN_95;
   wire [3:0] XLXN_96;
   wire [3:0] XLXN_97;
   wire XLXN_105;
   
   cnt60 cnt60_t (.ce(XLXN_95), .clk(clk_int), .clr(rst_int),
         .lsbsec(XLXN_96[3:0]), .msbsec(XLXN_97[3:0]));
   dcm1 dcm1_t (.CLKIN_IN(clk), .CLK0_OUT(clk_int));
   decode decode_t (.binary(XLXN_35[3:0]), .one_hot(XLXN_36[9:0]));
   hex2led hex2led1 (.hex(XLXN_96[3:0]), .led(onesout[6:0]));
   hex2led hex2led2 (.hex(XLXN_97[3:0]), .led(tensout[6:0]));
   outs3 out3_t (.inputs(XLXN_36[9:0]), .outs(tenthsout[9:0]));
   stmach_v stmach_t (.clk(clk_int), .reset(XLXN_3), .strtstop(XLXN_5),
         .clkout(clken_int), .rst(rst_int));
   tenths tenths_t (.AINIT(rst_int), .CE(clken_int), .CLK(clk_int),
         .Q(XLXN_35[3:0]), .Q_THRESH0(XLXN_105));
   INV XLXI_9 (.I(XLXN_2), .O(XLXN_3));
   IBUF XLXI_10 (.I(reset), .O(XLXN_2));
   // synthesis attribute IOSTANDARD of XLXI_10 is "LVTTL"
   IBUF XLXI_11 (.I(starstop), .O(XLXN_5));
   // synthesis attribute IOSTANDARD of XLXI_11 is "LVTTL"
   AND2 XLXI_22 (.I0(clken_int), .I1(XLXN_105), .O(XLXN_95));
endmodule