stopwatch.syr

FPGA-CPLD_DesignTool(8-9-10)源代码

    | Outputs            | 2                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | 000001                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred   1 Finite State Machine(s).
Unit <stmach_v> synthesized.


Synthesizing Unit <outs3>.
    Related source file is outs3.vf.
Unit <outs3> synthesized.


Synthesizing Unit <hex2led>.
    Related source file is C:/workstation/ISE      2004-05-13/CD/Example-9-1/watch_sc_v6/hex2led.vhd.
    Found 16x7-bit ROM for signal <led>.
    Summary:
	inferred   1 ROM(s).
Unit <hex2led> synthesized.


Synthesizing Unit <decode>.
    Related source file is C:/workstation/ISE      2004-05-13/CD/Example-9-1/watch_sc_v6/decode.vhd.
    Found 16x10-bit ROM for signal <one_hot>.
    Summary:
	inferred   1 ROM(s).
Unit <decode> synthesized.


Synthesizing Unit <dcm1>.
    Related source file is dcm1.v.
Unit <dcm1> synthesized.


Synthesizing Unit <cnt60>.
    Related source file is cnt60.vf.
Unit <cnt60> synthesized.


Synthesizing Unit <stopwatch>.
    Related source file is stopwatch.vf.
Unit <stopwatch> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <sreg> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 3
 16x10-bit ROM                     : 1
 16x7-bit ROM                      : 2
# Registers                        : 6
 1-bit register                    : 6

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "tenths.ngo" is up to date.
Loading core <tenths> for timing and area information for instance <tenths_t>.

Optimizing unit <stopwatch> ...

Optimizing unit <outs3> ...

Optimizing unit <CD4CE_MXILINX_cnt60> ...

Optimizing unit <FTCE_MXILINX_cnt60> ...

Optimizing unit <CB4CE_MXILINX_cnt60> ...
Loading device for application Xst from file '2v40.nph' in environment C:/eda/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block stopwatch, actual ratio is 11.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : stopwatch.ngr
Top Level Output File Name         : stopwatch
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 27

Macro Statistics :
# ROMs                             : 3
#      16x10-bit ROM               : 1
#      16x7-bit ROM                : 2

Cell Usage :
# BELS                             : 89
#      AND2                        : 8
#      AND2b1                      : 1
#      AND3                        : 2
#      AND4                        : 2
#      AND4b2                      : 1
#      GND                         : 2
#      INV                         : 14
#      LUT2_L                      : 1
#      LUT3                        : 4
#      LUT4                        : 37
#      MUXCY                       : 3
#      OR2                         : 2
#      VCC                         : 1
#      XOR2                        : 7
#      XORCY                       : 4
# FlipFlops/Latches                : 20
#      FDC                         : 5
#      FDCE                        : 11
#      FDE                         : 2
#      FDP                         : 1
#      FDPE                        : 1
# Clock Buffers                    : 1
#      BUFG                        : 1
# IO Buffers                       : 27
#      IBUF                        : 2
#      IBUFG                       : 1
#      OBUF                        : 24
# DCMs                             : 1
#      DCM                         : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v40fg256-5 

 Number of Slices:                      29  out of    256    11%  
 Number of Slice Flip Flops:            20  out of    512     3%  
 Number of 4 input LUTs:                42  out of    512     8%  
 Number of bonded IOBs:                 27  out of     88    30%  
 Number of GCLKs:                        1  out of     16     6%  
 Number of DCMs:                         1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | dcm1_t_DCM_INST:CLK0   | 20    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 4.458ns (Maximum Frequency: 224.316MHz)
   Minimum input arrival time before clock: 2.092ns
   Maximum output required time after clock: 6.844ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               4.458ns (Levels of Logic = 6)
  Source:            tenths_t/BU28 (FF)
  Destination:       tenths_t/BU10 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: tenths_t/BU28 to tenths_t/BU10
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDPE:C->Q            11   0.494   0.790  BU28 (Q<0>)
     LUT4:I0->O            1   0.382   0.000  BU22 (N98)
     MUXCY:S->O            1   0.259   0.000  BU23 (N100)
     MUXCY:CI->O           1   0.046   0.000  BU31 (N105)
     MUXCY:CI->O           0   0.046   0.000  BU39 (N110)
     XORCY:CI->O           3   1.107   0.630  BU47 (N5)
     LUT4:I0->O            1   0.382   0.000  BU9 (N46)
     FDE:D                     0.322          BU10
    ----------------------------------------
    Total                      4.458ns (3.038ns logic, 1.420ns route)
                                       (68.1% logic, 31.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Offset:              2.092ns (Levels of Logic = 2)
  Source:            starstop (PAD)
  Destination:       stmach_t_sreg_FFd1 (FF)
  Destination Clock: clk rising

  Data Path: starstop to stmach_t_sreg_FFd1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             5   0.718   0.670  XLXI_11 (XLXN_5)
     LUT3:I0->O            1   0.382   0.000  stmach_t_sreg_FFd1-In1 (stmach_t_sreg_FFd1-In)
     FDC:D                     0.322          stmach_t_sreg_FFd1
    ----------------------------------------
    Total                      2.092ns (1.422ns logic, 0.670ns route)
                                       (68.0% logic, 32.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              6.844ns (Levels of Logic = 4)
  Source:            tenths_t/BU36 (FF)
  Destination:       tenthsout<9> (PAD)
  Source Clock:      clk rising

  Data Path: tenths_t/BU36 to tenthsout<9>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            11   0.494   0.790  BU36 (Q<1>)
     end scope: 'tenths_t'
     LUT4:I1->O            1   0.382   0.450  decode_t_Mrom_one_hot_inst_lut4_01 (XLXN_36<0>)
     INV:I->O              1   0.382   0.450  out3_t_I11 (out3_t_XLXN_21)
     OBUF:I->O                 3.896          out3_t_I10 (tenthsout<0>)
    ----------------------------------------
    Total                      6.844ns (5.154ns logic, 1.690ns route)
                                       (75.3% logic, 24.7% route)

=========================================================================
CPU : 5.96 / 6.75 s | Elapsed : 6.00 / 7.00 s
 
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Total memory usage is 63852 kilobytes