stopwatch.syr

FPGA-CPLD_DesignTool(8-9-10)源代码

Release 6.2i - xst G.30
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.39 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.39 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: stopwatch.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : stopwatch.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : stopwatch
Output Format                      : NGC
Target Device                      : xc2v40-5-fg256

---- Source Options
Top Module Name                    : stopwatch
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : stopwatch.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:Xst:878 - tenths.v line 108: Unrecognized directive. Ignoring.
Compiling source file "cnt60.vf"
Module <FTCE_MXILINX_cnt60> compiled
Module <CB4CE_MXILINX_cnt60> compiled
Module <CD4CE_MXILINX_cnt60> compiled
Module <cnt60> compiled
Compiling source file "dcm1.v"
Module <dcm1> compiled
Compiling source file "outs3.vf"
Module <outs3> compiled
Compiling source file "tenths.v"
Module <tenths> compiled
Compiling source file "stopwatch.vf"
Module <stopwatch> compiled
No errors in compilation
Analysis of file <stopwatch.prj> succeeded.
 
WARNING:HDLParsers:3215 - Unit work/STMACH_V is now defined in a different file: was c:/example-9-1/watch_sc/STMACH_V.vhd, now is C:/workstation/ISE      2004-05-13/CD/Example-9-1/watch_sc_v6/STMACH_V.vhd
WARNING:HDLParsers:3215 - Unit work/STMACH_V/BEHAVIOR is now defined in a different file: was c:/example-9-1/watch_sc/STMACH_V.vhd, now is C:/workstation/ISE      2004-05-13/CD/Example-9-1/watch_sc_v6/STMACH_V.vhd
WARNING:HDLParsers:3215 - Unit work/DECODE is now defined in a different file: was c:/example-9-1/watch_sc/decode.vhd, now is C:/workstation/ISE      2004-05-13/CD/Example-9-1/watch_sc_v6/decode.vhd
WARNING:HDLParsers:3215 - Unit work/DECODE/BEHAVIORAL is now defined in a different file: was c:/example-9-1/watch_sc/decode.vhd, now is C:/workstation/ISE      2004-05-13/CD/Example-9-1/watch_sc_v6/decode.vhd
WARNING:HDLParsers:3215 - Unit work/HEX2LED is now defined in a different file: was c:/example-9-1/watch_sc/hex2led.vhd, now is C:/workstation/ISE      2004-05-13/CD/Example-9-1/watch_sc_v6/hex2led.vhd
WARNING:HDLParsers:3215 - Unit work/HEX2LED/BEHAVIORAL is now defined in a different file: was c:/example-9-1/watch_sc/hex2led.vhd, now is C:/workstation/ISE      2004-05-13/CD/Example-9-1/watch_sc_v6/hex2led.vhd
Compiling vhdl file C:/workstation/ISE      2004-05-13/CD/Example-9-1/watch_sc_v6/STMACH_V.vhd in Library work.
Architecture behavior of Entity stmach_v is up to date.
Compiling vhdl file C:/workstation/ISE      2004-05-13/CD/Example-9-1/watch_sc_v6/decode.vhd in Library work.
Architecture behavioral of Entity decode is up to date.
Compiling vhdl file C:/workstation/ISE      2004-05-13/CD/Example-9-1/watch_sc_v6/hex2led.vhd in Library work.
Architecture behavioral of Entity hex2led is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <stopwatch>.
Module <stopwatch> is correct for synthesis.
 
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <XLXI_10> in unit <stopwatch>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <XLXI_11> in unit <stopwatch>.
    Set property "resynthesize = true" for unit <stopwatch>.
Analyzing module <cnt60>.
Module <cnt60> is correct for synthesis.
 
    Set user-defined property "HU_SET =  XLXI_2_4" for instance <XLXI_2> in unit <cnt60>.
    Set user-defined property "HU_SET =  XLXI_3_5" for instance <XLXI_3> in unit <cnt60>.
Analyzing module <CD4CE_MXILINX_cnt60>.
Module <CD4CE_MXILINX_cnt60> is correct for synthesis.
 
    Set user-defined property "INIT =  0" for instance <I_Q0> in unit <CD4CE_MXILINX_cnt60>.
    Set user-defined property "INIT =  0" for instance <I_Q1> in unit <CD4CE_MXILINX_cnt60>.
    Set user-defined property "INIT =  0" for instance <I_Q2> in unit <CD4CE_MXILINX_cnt60>.
    Set user-defined property "INIT =  0" for instance <I_Q3> in unit <CD4CE_MXILINX_cnt60>.
Analyzing module <FDCE>.
Analyzing module <AND3>.
Analyzing module <XOR2>.
Analyzing module <AND2B1>.
Analyzing module <AND4B2>.
Analyzing module <CB4CE_MXILINX_cnt60>.
Module <CB4CE_MXILINX_cnt60> is correct for synthesis.
 
    Set user-defined property "HU_SET =  I_Q0_0" for instance <I_Q0> in unit <CB4CE_MXILINX_cnt60>.
    Set user-defined property "HU_SET =  I_Q1_1" for instance <I_Q1> in unit <CB4CE_MXILINX_cnt60>.
    Set user-defined property "HU_SET =  I_Q2_2" for instance <I_Q2> in unit <CB4CE_MXILINX_cnt60>.
    Set user-defined property "HU_SET =  I_Q3_3" for instance <I_Q3> in unit <CB4CE_MXILINX_cnt60>.
Analyzing module <FTCE_MXILINX_cnt60>.
Module <FTCE_MXILINX_cnt60> is correct for synthesis.
 
    Set user-defined property "RLOC =  X0Y0" for instance <I_36_35> in unit <FTCE_MXILINX_cnt60>.
    Set user-defined property "INIT =  0" for instance <I_36_35> in unit <FTCE_MXILINX_cnt60>.
Analyzing module <VCC>.
Analyzing module <OR2>.
Analyzing module <AND4>.
Analyzing module <dcm1>.
Module <dcm1> is correct for synthesis.
 
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_INST> in unit <dcm1>.
    Set user-defined property "CLKDV_DIVIDE =  2" for instance <DCM_INST> in unit <dcm1>.
    Set user-defined property "CLKFX_DIVIDE =  1" for instance <DCM_INST> in unit <dcm1>.
    Set user-defined property "CLKFX_MULTIPLY =  4" for instance <DCM_INST> in unit <dcm1>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <DCM_INST> in unit <dcm1>.
    Set user-defined property "CLKIN_PERIOD =  20" for instance <DCM_INST> in unit <dcm1>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <DCM_INST> in unit <dcm1>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <dcm1>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <dcm1>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <dcm1>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_INST> in unit <dcm1>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <DCM_INST> in unit <dcm1>.
    Set user-defined property "STARTUP_WAIT =  TRUE" for instance <DCM_INST> in unit <dcm1>.
Analyzing module <DCM>.
Analyzing module <IBUFG>.
Analyzing module <BUFG>.
Analyzing Entity <decode> (Architecture <behavioral>).
Entity <decode> analyzed. Unit <decode> generated.

Analyzing Entity <hex2led> (Architecture <behavioral>).
Entity <hex2led> analyzed. Unit <hex2led> generated.

Analyzing module <outs3>.
Module <outs3> is correct for synthesis.
 
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <I1> in unit <outs3>.
    Set user-defined property "SLEW =  SLOW" for instance <I1> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <I1> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <I2> in unit <outs3>.
    Set user-defined property "SLEW =  SLOW" for instance <I2> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <I2> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <I3> in unit <outs3>.
    Set user-defined property "SLEW =  SLOW" for instance <I3> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <I3> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <I4> in unit <outs3>.
    Set user-defined property "SLEW =  SLOW" for instance <I4> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <I4> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <I5> in unit <outs3>.
    Set user-defined property "SLEW =  SLOW" for instance <I5> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <I5> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <I6> in unit <outs3>.
    Set user-defined property "SLEW =  SLOW" for instance <I6> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <I6> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <I7> in unit <outs3>.
    Set user-defined property "SLEW =  SLOW" for instance <I7> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <I7> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <I8> in unit <outs3>.
    Set user-defined property "SLEW =  SLOW" for instance <I8> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <I8> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <I9> in unit <outs3>.
    Set user-defined property "SLEW =  SLOW" for instance <I9> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <I9> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <I10> in unit <outs3>.
    Set user-defined property "SLEW =  SLOW" for instance <I10> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <I10> in unit <outs3>.
Analyzing module <OBUF>.
Analyzing Entity <stmach_v> (Architecture <behavior>).
Entity <stmach_v> analyzed. Unit <stmach_v> generated.

Analyzing module <tenths>.
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Analyzing module <INV>.
Analyzing module <IBUF>.
Analyzing module <AND2>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <FTCE_MXILINX_cnt60>.
    Related source file is cnt60.vf.
Unit <FTCE_MXILINX_cnt60> synthesized.


Synthesizing Unit <CB4CE_MXILINX_cnt60>.
    Related source file is cnt60.vf.
Unit <CB4CE_MXILINX_cnt60> synthesized.


Synthesizing Unit <CD4CE_MXILINX_cnt60>.
    Related source file is cnt60.vf.
Unit <CD4CE_MXILINX_cnt60> synthesized.


Synthesizing Unit <stmach_v>.
    Related source file is C:/workstation/ISE      2004-05-13/CD/Example-9-1/watch_sc_v6/STMACH_V.vhd.
    Found finite state machine <FSM_0> for signal <sreg>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 11                                             |
    | Inputs             | 1                                              |