tenths.sym

FPGA-CPLD_DesignTool(8-9-10)源代码

VERSION 5
BEGIN SYMBOL tenths
SYMBOLTYPE BLOCK
TIMESTAMP 2004 10 12 14 54 44
SYMPIN 0 176 Input CE
SYMPIN 0 208 Input CLK
SYMPIN 480 80 Output Q_THRESH0
SYMPIN 480 176 Output Q(3:0)
SYMPIN 288 304 Input AINIT
RECTANGLE N 32 0 448 272 
BEGIN DISPLAY 36 176 PIN CE ATTR PinName
    FONT 24 "Arial"
END DISPLAY
LINE N 0 176 32 176 
BEGIN DISPLAY 36 208 PIN CLK ATTR PinName
    FONT 24 "Arial"
END DISPLAY
LINE N 0 208 32 208 
BEGIN DISPLAY 444 80 PIN Q_THRESH0 ATTR PinName
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
LINE N 448 80 480 80 
BEGIN DISPLAY 444 176 PIN Q(3:0) ATTR PinName
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
BEGIN LINE W 448 176 480 176 
END LINE
BEGIN DISPLAY 288 268 PIN AINIT ATTR PinName
    ALIGNMENT BCENTER
    FONT 24 "Arial"
END DISPLAY
LINE N 288 272 288 304 
END SYMBOL