tenths.asy

来自「FPGA-CPLD_DesignTool(8-9-10)源代码」· ASY 代码 · 共 25 行

Version 4
SymbolType BLOCK
RECTANGLE Normal 32 0 448 272
PIN 0 176  LEFT 36
PINATTR PinName CE
PINATTR Polarity IN
LINE Normal 0 176 32 176
PIN 0 208  LEFT 36
PINATTR PinName CLK
PINATTR Polarity IN
LINE Normal 0 208 32 208
PIN 480 80  RIGHT 36
PINATTR PinName Q_THRESH0
PINATTR Polarity OUT
LINE Normal 448 80 480 80
PIN 480 176  RIGHT 36
PINATTR PinName Q[3:0]
PINATTR Polarity OUT
LINE Wide 448 176 480 176
PIN 288 304  BOTTOM 36
PINATTR PinName AINIT
PINATTR Polarity IN
LINE Normal 288 272 288 304
LINE Normal 288 272 288 304