stopwatch.mrp

FPGA-CPLD_DesignTool(8-9-10)源代码

Release 6.2i Map G.30
Xilinx Mapping Report File for Design 'stopwatch'

Design Information
------------------
Command Line   : C:/eda/Xilinx/bin/nt/map.exe -intstyle ise -p xc2v40-fg256-5
-cm area -pr b -k 4 -c 100 -tx off -o stopwatch_map.ncd stopwatch.ngd
stopwatch.pcf 
Target Device  : x2v40
Target Package : fg256
Target Speed   : -5
Mapper Version : virtex2 -- $Revision: 1.16.8.1 $
Mapped Date    : Tue Oct 12 23:20:55 2004

Design Summary
--------------
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:          20 out of     512    3%
  Number of 4 input LUTs:              53 out of     512   10%
Logic Distribution:
  Number of occupied Slices:           31 out of     256   12%
  Number of Slices containing only related logic:      31 out of      31  100%
  Number of Slices containing unrelated logic:          0 out of      31    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:             53 out of     512   10%

  Number of bonded IOBs:               27 out of      88   30%
  Number of GCLKs:                      1 out of      16    6%
  Number of DCMs:                       1 out of       4   25%

   Number of RPM macros:            1
Total equivalent gate count for design:  7,502
Additional JTAG gate count for IOBs:  1,296
Peak Memory Usage:  62 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Additional Device Resource Counts

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
   slice components.  The resulting carry chain will have suboptimal timing.
   	tenths_t/BU23
   	tenths_t/BU31

Section 3 - Informational
-------------------------
INFO:LIT:95 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
   BUFG symbol "dcm1_t_CLK0_BUFG_INST" (output signal=clk_int)

Section 4 - Removed Logic Summary
---------------------------------
   4 block(s) removed
   3 block(s) optimized away
   3 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections.  If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented.  This
indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).

The signal "cnt60_t_XLXI_2/CEO" is sourceless and has been removed.
The signal "cnt60_t_XLXI_3/TC" is sourceless and has been removed.
 Sourceless block "cnt60_t_XLXI_3/I_36_67" (AND) removed.
  The signal "cnt60_t_XLXI_3/CEO" is sourceless and has been removed.
Unused block "cnt60_t_XLXI_2/I_36_99" (AND) removed.
Unused block "cnt60_t_XLXI_3/I_36_31" (AND) removed.
Unused block "tenths_t/VCC" (ONE) removed.

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		cnt60_t_XLXI_3/I_36_58
GND 		tenths_t/GND

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| clk                                | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| onesout<0>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| onesout<1>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| onesout<2>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| onesout<3>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| onesout<4>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| onesout<5>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| onesout<6>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| reset                              | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| starstop                           | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| tensout<0>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| tensout<1>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| tensout<2>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| tensout<3>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| tensout<4>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| tensout<5>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| tensout<6>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| tenthsout<0>                       | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| tenthsout<1>                       | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| tenthsout<2>                       | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| tenthsout<3>                       | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| tenthsout<4>                       | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| tenthsout<5>                       | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| tenthsout<6>                       | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| tenthsout<7>                       | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| tenthsout<8>                       | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| tenthsout<9>                       | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
+------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------
tenths_t/hset                           
cnt60_t_XLXI_3_5                        
cnt60_t_XLXI_3/cnt60_t_XLXI_3_I_Q3_3    
cnt60_t_XLXI_3/cnt60_t_XLXI_3_I_Q2_2    
cnt60_t_XLXI_3/cnt60_t_XLXI_3_I_Q1_1    
cnt60_t_XLXI_3/cnt60_t_XLXI_3_I_Q0_0    
cnt60_t_XLXI_2_4                        

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group Summary
------------------------------
No area groups were found in this design.

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.

Section 11 - Timing Report
--------------------------
This design was not run using timing mode.

Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings

Section 13 - Additional Device Resource Counts
----------------------------------------------
Number of JTAG Gates for IOBs = 27
Number of Equivalent Gates for Design = 7,502
Number of RPM Macros = 1
Number of Hard Macros = 0
CAPTUREs = 0
BSCANs = 0
STARTUPs = 0
PCILOGICs = 0
DCMs = 1
GCLKs = 1
ICAPs = 0
18X18 Multipliers = 0
Block RAMs = 0
TBUFs = 0
Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 2
IOB Dual-Rate Flops not driven by LUTs = 0
IOB Dual-Rate Flops = 0
IOB Slave Pads = 0
IOB Master Pads = 0
IOB Latches not driven by LUTs = 0
IOB Latches = 0
IOB Flip Flops not driven by LUTs = 0
IOB Flip Flops = 0
Unbonded IOBs = 0
Bonded IOBs = 27
Total Shift Registers = 0
Static Shift Registers = 0
Dynamic Shift Registers = 0
16x1 ROMs = 0
16x1 RAMs = 0
32x1 RAMs = 0
Dual Port RAMs = 0
MUXFs = 0
MULT_ANDs = 0
4 input LUTs used as Route-Thrus = 0
4 input LUTs = 53
Slice Latches not driven by LUTs = 0
Slice Latches = 0
Slice Flip Flops not driven by LUTs = 2
Slice Flip Flops = 20
Slices = 31
Number of LUT signals with 4 loads = 3
Number of LUT signals with 3 loads = 0
Number of LUT signals with 2 loads = 3
Number of LUT signals with 1 load = 44
NGM Average fanout of LUT = 1.47
NGM Maximum fanout of LUT = 6
NGM Average fanin for LUT = 3.2642
Number of LUT symbols = 53
Number of IPAD symbols = 3
Number of IBUF symbols = 3
Number of DCM symbols = 1