stmach_v.sym

来自「FPGA-CPLD_DesignTool(8-9-10)源代码」· SYM 代码 · 共 38 行

VERSION 5
BEGIN SYMBOL 
SYMBOLTYPE BLOCK
TIMESTAMP 2004 10 12 14 52 54
SYMPIN 0 -160 Input CLK
SYMPIN 0 -96 Input reset
SYMPIN 0 -32 Input strtstop
SYMPIN 384 -160 Output clkout
SYMPIN 384 -32 Output rst
RECTANGLE N 64 -192 320 0 
BEGIN DISPLAY 192 -200 ATTR SymbolName
    ALIGNMENT BCENTER
    FONT 56 "Arial"
END DISPLAY
LINE N 64 -160 0 -160 
BEGIN DISPLAY 72 -160 PIN CLK ATTR PinName
    FONT 24 "Arial"
END DISPLAY
LINE N 64 -96 0 -96 
BEGIN DISPLAY 72 -96 PIN reset ATTR PinName
    FONT 24 "Arial"
END DISPLAY
LINE N 64 -32 0 -32 
BEGIN DISPLAY 72 -32 PIN strtstop ATTR PinName
    FONT 24 "Arial"
END DISPLAY
LINE N 320 -160 384 -160 
BEGIN DISPLAY 312 -160 PIN clkout ATTR PinName
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
LINE N 320 -32 384 -32 
BEGIN DISPLAY 312 -32 PIN rst ATTR PinName
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
END SYMBOL