stopwatch.twr

FPGA-CPLD_DesignTool(8-9-10)源代码

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Release 6.2i Trace G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

C:/eda/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml stopwatch
stopwatch.ncd -o stopwatch.twr stopwatch.pcf


Design file:              stopwatch.ncd
Physical constraint file: stopwatch.pcf
Device,speed:             xc2v40,-5 (PRODUCTION 1.118 2004-03-12, STEPPING level 1)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
starstop    |    3.558(R)|   -2.578(R)|clk_int           |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
onesout<0>  |    5.254(R)|clk_int           |   0.000|
onesout<1>  |    5.502(R)|clk_int           |   0.000|
onesout<2>  |    5.566(R)|clk_int           |   0.000|
onesout<3>  |    5.484(R)|clk_int           |   0.000|
onesout<4>  |    5.572(R)|clk_int           |   0.000|
onesout<5>  |    5.859(R)|clk_int           |   0.000|
onesout<6>  |    5.804(R)|clk_int           |   0.000|
tensout<0>  |    5.749(R)|clk_int           |   0.000|
tensout<1>  |    5.334(R)|clk_int           |   0.000|
tensout<2>  |    5.544(R)|clk_int           |   0.000|
tensout<3>  |    5.544(R)|clk_int           |   0.000|
tensout<4>  |    6.117(R)|clk_int           |   0.000|
tensout<5>  |    6.165(R)|clk_int           |   0.000|
tensout<6>  |    6.031(R)|clk_int           |   0.000|
tenthsout<0>|    5.744(R)|clk_int           |   0.000|
tenthsout<1>|    5.571(R)|clk_int           |   0.000|
tenthsout<2>|    5.281(R)|clk_int           |   0.000|
tenthsout<3>|    5.724(R)|clk_int           |   0.000|
tenthsout<4>|    5.749(R)|clk_int           |   0.000|
tenthsout<5>|    5.264(R)|clk_int           |   0.000|
tenthsout<6>|    5.555(R)|clk_int           |   0.000|
tenthsout<7>|    5.259(R)|clk_int           |   0.000|
tenthsout<8>|    5.733(R)|clk_int           |   0.000|
tenthsout<9>|    5.540(R)|clk_int           |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    4.204|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Tue Oct 12 23:21:00 2004
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Peak Memory Usage: 44 MB