cnt60.sym

FPGA-CPLD_DesignTool(8-9-10)源代码

VERSION 5
BEGIN SYMBOL 
SYMBOLTYPE BLOCK
TIMESTAMP 2004 10 12 14 47 20
SYMPIN 0 -160 Input ce
SYMPIN 0 -96 Input clk
SYMPIN 0 -32 Input clr
SYMPIN 384 -160 Output lsbsec(3:0)
SYMPIN 384 -32 Output msbsec(3:0)
RECTANGLE N 64 -192 320 0 
BEGIN DISPLAY 192 -200 ATTR SymbolName
    ALIGNMENT BCENTER
    FONT 56 "Arial"
END DISPLAY
LINE N 64 -160 0 -160 
BEGIN DISPLAY 72 -160 PIN ce ATTR PinName
    FONT 24 "Arial"
END DISPLAY
LINE N 64 -96 0 -96 
BEGIN DISPLAY 72 -96 PIN clk ATTR PinName
    FONT 24 "Arial"
END DISPLAY
LINE N 64 -32 0 -32 
BEGIN DISPLAY 72 -32 PIN clr ATTR PinName
    FONT 24 "Arial"
END DISPLAY
LINE N 320 -160 384 -160 
BEGIN DISPLAY 312 -160 PIN lsbsec(3:0) ATTR PinName
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
RECTANGLE N 320 -172 384 -148 
LINE N 320 -32 384 -32 
BEGIN DISPLAY 312 -32 PIN msbsec(3:0) ATTR PinName
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
RECTANGLE N 320 -44 384 -20 
END SYMBOL