watch_sc.npl

FPGA-CPLD_DesignTool(8-9-10)源代码

JDF G
// Created by Project Navigator ver 1.0
PROJECT watch_sc
DESIGN watch_sc
DEVFAM virtex2
DEVFAMTIME 0
DEVICE xc2v40
DEVICETIME 0
DEVPKG fg256
DEVPKGTIME 0
DEVSPEED -5
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE Schematic
TOPLEVELMODULETYPETIME 1097592132
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL Verilog
GENERATEDSIMULATIONMODELTIME 1097592132
SOURCE stopwatch.sch
SOURCE cnt60.sch
SOURCE decode.vhd
SOURCE hex2led.vhd
SOURCE outs3.sch
SOURCE STMACH_V.vhd
SOURCE tenths.xco
SOURCE dcm1.xaw
[STATUS-ALL]
stopwatch.ngcFile=WARNINGS,1097594446
stopwatch.ngdFile=WARNINGS,1097594453
[STRATEGY-LIST]
Normal=True