outs3.vf

FPGA-CPLD_DesignTool(8-9-10)源代码

// Verilog model created from schematic outs3.sch - Thu Dec 05 17:54:29 2002


`timescale 1ns / 1ps

module outs3(inputs, outs);

 input [9:0] inputs;
output [9:0] outs;

wire XLXN_12;
wire XLXN_13;
wire XLXN_14;
wire XLXN_15;
wire XLXN_16;
wire XLXN_17;
wire XLXN_18;
wire XLXN_19;
wire XLXN_20;
wire XLXN_21;

INV I11 (.I(inputs[0]), .O(XLXN_21));
INV I12 (.I(inputs[9]), .O(XLXN_12));
INV I13 (.I(inputs[8]), .O(XLXN_13));
INV I14 (.I(inputs[7]), .O(XLXN_14));
INV I15 (.I(inputs[6]), .O(XLXN_15));
INV I16 (.I(inputs[5]), .O(XLXN_16));
INV I17 (.I(inputs[4]), .O(XLXN_17));
INV I18 (.I(inputs[3]), .O(XLXN_18));
INV I19 (.I(inputs[2]), .O(XLXN_19));
INV I20 (.I(inputs[1]), .O(XLXN_20));
OBUF I10 (.I(XLXN_21), .O(outs[0]));
   // synthesis attribute DRIVE of I10 is "12"
   // synthesis attribute IOSTANDARD of I10 is "LVTTL"
   // synthesis attribute SLEW of I10 is "SLOW"
OBUF I9 (.I(XLXN_20), .O(outs[1]));
   // synthesis attribute DRIVE of I9 is "12"
   // synthesis attribute IOSTANDARD of I9 is "LVTTL"
   // synthesis attribute SLEW of I9 is "SLOW"
OBUF I8 (.I(XLXN_19), .O(outs[2]));
   // synthesis attribute DRIVE of I8 is "12"
   // synthesis attribute IOSTANDARD of I8 is "LVTTL"
   // synthesis attribute SLEW of I8 is "SLOW"
OBUF I7 (.I(XLXN_18), .O(outs[3]));
   // synthesis attribute DRIVE of I7 is "12"
   // synthesis attribute IOSTANDARD of I7 is "LVTTL"
   // synthesis attribute SLEW of I7 is "SLOW"
OBUF I6 (.I(XLXN_17), .O(outs[4]));
   // synthesis attribute DRIVE of I6 is "12"
   // synthesis attribute IOSTANDARD of I6 is "LVTTL"
   // synthesis attribute SLEW of I6 is "SLOW"
OBUF I5 (.I(XLXN_16), .O(outs[5]));
   // synthesis attribute DRIVE of I5 is "12"
   // synthesis attribute IOSTANDARD of I5 is "LVTTL"
   // synthesis attribute SLEW of I5 is "SLOW"
OBUF I4 (.I(XLXN_15), .O(outs[6]));
   // synthesis attribute DRIVE of I4 is "12"
   // synthesis attribute IOSTANDARD of I4 is "LVTTL"
   // synthesis attribute SLEW of I4 is "SLOW"
OBUF I3 (.I(XLXN_14), .O(outs[7]));
   // synthesis attribute DRIVE of I3 is "12"
   // synthesis attribute IOSTANDARD of I3 is "LVTTL"
   // synthesis attribute SLEW of I3 is "SLOW"
OBUF I2 (.I(XLXN_13), .O(outs[8]));
   // synthesis attribute DRIVE of I2 is "12"
   // synthesis attribute IOSTANDARD of I2 is "LVTTL"
   // synthesis attribute SLEW of I2 is "SLOW"
OBUF I1 (.I(XLXN_12), .O(outs[9]));
   // synthesis attribute DRIVE of I1 is "12"
   // synthesis attribute IOSTANDARD of I1 is "LVTTL"
   // synthesis attribute SLEW of I1 is "SLOW"
endmodule