stmach_v.plg

来自「FPGA-CPLD_DesignTool(8-9-10)源代码」· PLG 代码 · 共 12 行

@P:  Worst Slack : 994.683
@P:  stmach_v|CLK - Estimated Frequency : 188.1 MHz
@P:  stmach_v|CLK - Requested Frequency : 1.0 MHz
@P:  stmach_v|CLK - Estimated Period : 5.317
@P:  stmach_v|CLK - Requested Period : 1000.000
@P:  stmach_v|CLK - Slack : 994.683
@P: stmach_v Part : xc2vp2ff672-7
@P: stmach_v I/O primitives : 4
@P: stmach_v I/O Register bits : 1
@P: stmach_v Register bits (Non I/O) : 6 (0%)
@P: stmach_v Total Luts : 7 (0%)