module_a.v

来自「FPGA-CPLD_DesignTool(8-9-10)源代码」· Verilog 代码 · 共 35 行

module module_a ( CLK_TOP, B2A_IN, TOP2A_IN, C2A_IN, MODA_DATA, 
		  MODA_CLK, MODA_OUT, A2B_OUT, A2TOP_OBUFT_I_OUT, A2C_OUT); 
input CLK_TOP ; 
input B2A_IN ; 
input TOP2A_IN ; 
input C2A_IN ; 
input MODA_DATA, MODA_CLK; 
output MODA_OUT; 
output A2B_OUT ; 
output A2TOP_OBUFT_I_OUT ; 
output A2C_OUT ; 
// add your declarations here 
reg Q0_OUT, Q1_OUT, Q2_OUT, Q3_OUT ; 
reg A2B_OUT, A2TOP_OBUFT_I_OUT, A2C_OUT ; 
reg MODA_OUT; 
wire AND4_OUT ; 
wire OR4_OUT ; 
// add your code here 
assign AND4_OUT = Q0_OUT && Q1_OUT && Q2_OUT && Q3_OUT ; 
assign OR4_OUT = Q0_OUT || Q1_OUT || Q2_OUT || Q3_OUT ; 
always @ (posedge CLK_TOP) 
begin : TOP_CLK 
  Q0_OUT <= MODA_DATA ; 
  Q2_OUT <= TOP2A_IN ; 
  MODA_OUT <= OR4_OUT ; 
  A2B_OUT <= AND4_OUT ; 
end 
always @ (posedge MODA_CLK) 
begin : CLK_MODA 
  Q1_OUT <= B2A_IN ; 
  Q3_OUT <= C2A_IN ; 
  A2TOP_OBUFT_I_OUT <= AND4_OUT ; 
  A2C_OUT <= OR4_OUT ; 
end 
endmodule