⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 top.srr

📁 FPGA-CPLD_DesignTool(8-9-10)源代码
💻 SRR
📖 第 1 页 / 共 2 页
字号:
MODA_OUT                Net      -            -       0.461     -           1         
moda_out_obuf           OBUF     I            In      -         0.910       -         
moda_out_obuf           OBUF     O            Out     4.067     4.977       -         
moda_out                Net      -            -       0.000     -           0         
moda_out                Port     moda_out     Out     -         4.977       -         
======================================================================================
Total path delay (propagation time + setup) of 4.977 is 4.516(90.7%) logic and 0.461(9.3%) route.




====================================
Detailed Report for Clock: top|moda_clk_pad
====================================



Starting Points with Worst Slack
********************************

                                 Starting                                                    Arrival            
Instance                         Reference            Type     Pin     Net                   Time        Slack  
                                 Clock                                                                          
----------------------------------------------------------------------------------------------------------------
instance_a.A2TOP_OBUFT_I_OUT     top|moda_clk_pad     FDR      Q       A2TOP_OBUFT_I_OUT     0.449       995.023
instance_a.Q3_OUT                top|moda_clk_pad     FD       Q       Q3_OUT                0.449       997.971
instance_a.Q1_OUT                top|moda_clk_pad     FD       Q       Q1_OUT                0.449       998.006
================================================================================================================


Ending Points with Worst Slack
******************************

                                 Starting                                                   Required            
Instance                         Reference            Type     Pin           Net            Time         Slack  
                                 Clock                                                                          
----------------------------------------------------------------------------------------------------------------
obuft_out                        top|moda_clk_pad     Port     obuft_out     obuft_out      1000.000     995.023
instance_a.A2TOP_OBUFT_I_OUT     top|moda_clk_pad     FDR      R             Q3_OUT_i       999.778      997.971
instance_a.A2C_OUT               top|moda_clk_pad     FDS      D             A2C_OUTs_i     999.707      998.006
instance_a.A2TOP_OBUFT_I_OUT     top|moda_clk_pad     FDR      D             A2B_OUTc       999.707      998.006
instance_a.A2C_OUT               top|moda_clk_pad     FDS      S             Q3_OUT         999.778      998.711
================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Requested Period:                        1000.000
    = Required time:                         1000.000

    - Propagation time:                      4.977
    = Slack (critical) :                     995.023

    Number of logic level(s):                1
    Starting point:                          instance_a.A2TOP_OBUFT_I_OUT / Q
    Ending point:                            obuft_out / obuft_out
    The start point is clocked by            top|moda_clk_pad [rising] on pin C
    The end   point is clocked by            top|moda_clk_pad [rising]

Instance / Net                             Pin           Pin               Arrival     No. of    
Name                             Type      Name          Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------
instance_a.A2TOP_OBUFT_I_OUT     FDR       Q             Out     0.449     0.449       -         
A2TOP_OBUFT_I_OUT                Net       -             -       0.461     -           1         
obuft_out_obuft                  OBUFT     I             In      -         0.910       -         
obuft_out_obuft                  OBUFT     O             Out     4.067     4.977       -         
obuft_out                        Net       -             -       0.000     -           0         
obuft_out                        Port      obuft_out     Out     -         4.977       -         
=================================================================================================
Total path delay (propagation time + setup) of 4.977 is 4.516(90.7%) logic and 0.461(9.3%) route.




====================================
Detailed Report for Clock: top|modb_clk_pad
====================================



Starting Points with Worst Slack
********************************

                                 Starting                                                    Arrival            
Instance                         Reference            Type     Pin     Net                   Time        Slack  
                                 Clock                                                                          
----------------------------------------------------------------------------------------------------------------
instance_b.B2TOP_OBUFT_T_OUT     top|modb_clk_pad     FDR      Q       B2TOP_OBUFT_T_OUT     0.449       995.221
instance_b.Q3_OUT                top|modb_clk_pad     FD       Q       Q3_OUT                0.449       997.971
instance_b.Q1_OUT                top|modb_clk_pad     FD       Q       Q1_OUT                0.449       998.006
================================================================================================================


Ending Points with Worst Slack
******************************

                                 Starting                                                  Required            
Instance                         Reference            Type     Pin           Net           Time         Slack  
                                 Clock                                                                         
---------------------------------------------------------------------------------------------------------------
obuft_out                        top|modb_clk_pad     Port     obuft_out     obuft_out     1000.000     995.221
instance_b.B2TOP_OBUFT_T_OUT     top|modb_clk_pad     FDR      R             Q3_OUT_i      999.778      997.971
instance_b.B2C_OUT               top|modb_clk_pad     FDR      D             B2C_OUTc      999.707      998.006
instance_b.B2TOP_OBUFT_T_OUT     top|modb_clk_pad     FDR      D             B2A_OUTc      999.707      998.006
instance_b.B2C_OUT               top|modb_clk_pad     FDR      R             Q3_OUT        999.778      998.711
===============================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Requested Period:                        1000.000
    = Required time:                         1000.000

    - Propagation time:                      4.779
    = Slack (non-critical) :                 995.221

    Number of logic level(s):                1
    Starting point:                          instance_b.B2TOP_OBUFT_T_OUT / Q
    Ending point:                            obuft_out / obuft_out
    The start point is clocked by            top|modb_clk_pad [rising] on pin C
    The end   point is clocked by            top|modb_clk_pad [rising]

Instance / Net                             Pin           Pin               Arrival     No. of    
Name                             Type      Name          Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------
instance_b.B2TOP_OBUFT_T_OUT     FDR       Q             Out     0.449     0.449       -         
B2TOP_OBUFT_T_OUT                Net       -             -       0.461     -           1         
obuft_out_obuft                  OBUFT     T             In      -         0.910       -         
obuft_out_obuft                  OBUFT     O             Out     3.869     4.779       -         
obuft_out                        Net       -             -       0.000     -           0         
obuft_out                        Port      obuft_out     Out     -         4.779       -         
=================================================================================================
Total path delay (propagation time + setup) of 4.779 is 4.318(90.4%) logic and 0.461(9.6%) route.




====================================
Detailed Report for Clock: top|modc_clk_pad
====================================



Starting Points with Worst Slack
********************************

                         Starting                                            Arrival            
Instance                 Reference            Type     Pin     Net           Time        Slack  
                         Clock                                                                  
------------------------------------------------------------------------------------------------
instance_c.C2TOP_OUT     top|modc_clk_pad     FDS      Q       C2TOP_OUT     0.449       995.023
instance_c.Q3_OUT        top|modc_clk_pad     FD       Q       Q3_OUT        0.449       997.971
instance_c.Q1_OUT        top|modc_clk_pad     FD       Q       Q1_OUT        0.449       998.006
================================================================================================


Ending Points with Worst Slack
******************************

                         Starting                                                    Required            
Instance                 Reference            Type     Pin           Net             Time         Slack  
                         Clock                                                                           
---------------------------------------------------------------------------------------------------------
mod_c_out                top|modc_clk_pad     Port     mod_c_out     mod_c_out       1000.000     995.023
instance_c.C2A_OUT       top|modc_clk_pad     FDR      R             Q3_OUT_i        999.778      997.971
instance_c.C2A_OUT       top|modc_clk_pad     FDR      D             C2A_OUTc        999.707      998.006
instance_c.C2TOP_OUT     top|modc_clk_pad     FDS      D             MODC_OUTs_i     999.707      998.006
instance_c.C2TOP_OUT     top|modc_clk_pad     FDS      S             Q3_OUT          999.778      998.711
=========================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Requested Period:                        1000.000
    = Required time:                         1000.000

    - Propagation time:                      4.977
    = Slack (critical) :                     995.023

    Number of logic level(s):                1
    Starting point:                          instance_c.C2TOP_OUT / Q
    Ending point:                            mod_c_out / mod_c_out
    The start point is clocked by            top|modc_clk_pad [rising] on pin C
    The end   point is clocked by            top|modc_clk_pad [rising]

Instance / Net                    Pin           Pin               Arrival     No. of    
Name                     Type     Name          Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------
instance_c.C2TOP_OUT     FDS      Q             Out     0.449     0.449       -         
C2TOP_OUT                Net      -             -       0.461     -           1         
mod_c_out_obuf           OBUF     I             In      -         0.910       -         
mod_c_out_obuf           OBUF     O             Out     4.067     4.977       -         
mod_c_out                Net      -             -       0.000     -           0         
mod_c_out                Port     mod_c_out     Out     -         4.977       -         
========================================================================================
Total path delay (propagation time + setup) of 4.977 is 4.516(90.7%) logic and 0.461(9.3%) route.



##### END OF TIMING REPORT #####]


---------------------------------------
Resource Usage Report for top 

Mapping to part: xc2v500fg256-6
Cell usage:
CLKDLL          1 use
FD              12 uses
FDR             8 uses
FDS             4 uses

I/O primitives: 12
IBUF           6 uses
IBUFG          1 use
OBUF           4 uses
OBUFT          1 use

BUFG           1 use

BUFGP          3 uses

I/O Register bits:                  0
Register bits not including I/Os:   24 (0%)

Global Clock Buffers: 4 of 16 (25%)


Mapping Summary:
Total  LUTs: 7 (0%)

Mapper successful!
Process took 0h:0m:3s realtime, 0h:0m:3s cputime
###########################################################]

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -