syn_incremental.prj

FPGA-CPLD_DesignTool(8-9-10)源代码

#-- Synplicity, Inc.
#-- Version 7.5.1     
#-- Project file D:\CD\EXAMPLE-8-2\synplify_syn\Syn_Incremental.prj
#-- Written on Wed Jun 02 01:53:41 2004


#add_file options
add_file -verilog "module_b.v"
add_file -verilog "module_c.v"
add_file -verilog "module_a.v"
add_file -verilog "virtex2.v"
add_file -verilog "top.v"
add_file -constraint "Syn_Incremental.sdc"


#implementation: "rev_1"
impl -add rev_1

#device options
set_option -technology VIRTEX2
set_option -part XC2V500
set_option -package FG256
set_option -speed_grade -6

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -use_fsm_explorer 0

#map options
set_option -frequency 1.000
set_option -fanout_limit 10000
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -update_models_cp 0
set_option -verification_mode 0
set_option -fixgatedclocks 0
set_option -modular 0
set_option -retiming 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "rev_1/top.edf"

#implementation attributes
set_option -vlog_std v2001
impl -active "rev_1"