syn_incremental.sdc

FPGA-CPLD_DesignTool(8-9-10)源代码

# Synplicity, Inc. constraint file
# D:\CD\Example-8-2\synplify_syn\Syn_Incremental.sdc
# Written on Wed Jun 02 01:36:04 2004
# by Synplify Pro, 7.5.1      Scope Editor

#
# Clocks
#

#
# Clock to Clock
#

#
# Inputs/Outputs
#
define_input_delay -disable      -default
define_output_delay -disable     -default
define_input_delay -disable      {dll_rst}
define_input_delay -disable      {ipad_dll_clk_in}
define_output_delay -disable     {mod_c_out}
define_input_delay -disable      {moda_clk_pad}
define_input_delay -disable      {moda_data}
define_output_delay -disable     {moda_out}
define_input_delay -disable      {modb_clk_pad}
define_input_delay -disable      {modb_data}
define_output_delay -disable     {modb_out}
define_input_delay -disable      {modc_clk_pad}
define_input_delay -disable      {modc_data}
define_output_delay -disable     {modc_out}
define_output_delay -disable     {obuft_out}
define_input_delay -disable      {top2a_c}
define_input_delay -disable      {top2b}

#
# Registers
#

#
# Multicycle Path
#

#
# False Path
#

#
# Delay Path
#

#
# Attributes
#
define_attribute -disable {instance_a} xc_area_group {rr#cc#rr#cc}

#
# Compile Points
#
define_compile_point           {v:work.module_a} -type {locked} -cpfile {}
define_compile_point           {v:work.module_b} -type {locked} -cpfile {}
define_compile_point           {v:work.module_c} -type {locked} -cpfile {}

#
# Other Constraints
#