module_b.vhd

来自「FPGA-CPLD_DesignTool(8-9-10)源代码」· VHDL 代码 · 共 40 行

library IEEE; 
use IEEE.std_logic_1164.all; 
entity module_b is port ( CLK_TOP : in std_logic; 
    A2B_IN: in std_logic; 
    TOP2B_IN: in std_logic; 
    A_AND_C_IN: in std_logic; 
    MODB_DATA : in std_logic; 
    MODB_CLK : in std_logic; 
    MODB_OUT : out std_logic; 
    B2A_OUT: out std_logic; 
    B2TOP_OBUFT_T_OUT: out std_logic; 
    B2C_OUT: out std_logic) ; 
end module_b; 
architecture modular of module_b is 
-- add your signal declarations here 
signal Q0_OUT, Q1_OUT, Q2_OUT, Q3_OUT : std_logic; 
signal AND4_OUT: std_logic ; 
signal OR4_OUT : std_logic; 
begin 
AND4_OUT <= Q0_OUT and Q1_OUT and Q2_OUT and Q3_OUT ; 
OR4_OUT <= Q0_OUT or Q1_OUT or Q2_OUT or Q3_OUT ; 
TOP_CLK: process(CLK_TOP) 
begin 
if (CLK_TOP 'event and CLK_TOP = '1') then
  Q0_OUT <= MODB_DATA ; 
  Q2_OUT <= TOP2B_IN ; 
  MODB_OUT <= OR4_OUT ; 
  B2A_OUT <= AND4_OUT ; 
end if; 
end process TOP_CLK; 
CLK_MODB: process(MODB_CLK) 
begin 
if (MODB_CLK 'event and MODB_CLK = '1') then 
  Q1_OUT <= A2B_IN ; 
  Q3_OUT <= A_AND_C_IN ; 
  B2TOP_OBUFT_T_OUT <= AND4_OUT ; 
  B2C_OUT <= OR4_OUT ; 
end if; 
end process CLK_MODB; 
end modular;