virtex2.vhd

FPGA-CPLD_DesignTool(8-9-10)源代码

   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_F_8 : component is true;
component IOBUF_LVTTL_S_12
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_S_12 : component is true;
component IOBUF_LVTTL_S_16
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_S_16 : component is true;
component IOBUF_LVTTL_S_2
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_S_2 : component is true;
component IOBUF_LVTTL_S_24
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_S_24 : component is true;
component IOBUF_LVTTL_S_4
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_S_4 : component is true;
component IOBUF_LVTTL_S_6
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_S_6 : component is true;
component IOBUF_LVTTL_S_8
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_S_8 : component is true;
component IOBUF_PCI33_3
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_PCI33_3 : component is true;
component IOBUF_PCI66_3
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_PCI66_3 : component is true;
component IOBUF_PCIX
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_PCIX : component is true;
component IOBUF_SSTL2_I
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_SSTL2_I : component is true;
component IOBUF_SSTL2_II
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_SSTL2_II : component is true;
component IOBUF_SSTL2_II_DCI
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_SSTL2_II_DCI : component is true;
component IOBUF_SSTL3_I
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_SSTL3_I : component is true;
component IOBUF_SSTL3_II
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_SSTL3_II : component is true;
component IOBUF_SSTL3_II_DCI
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_SSTL3_II_DCI : component is true;
component IOBUF_S_12
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_S_12 : component is true;
component IOBUF_S_16
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_S_16 : component is true;
component IOBUF_S_2
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_S_2 : component is true;
component IOBUF_S_24
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_S_24 : component is true;
component IOBUF_S_4
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_S_4 : component is true;
component IOBUF_S_6
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_S_6 : component is true;
component IOBUF_S_8
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_S_8 : component is true;
component KEEPER
 port (
   O : inout std_logic
 );
end component;
attribute syn_black_box of KEEPER : component is true;
attribute syn_noprune of KEEPER : component is true;
component LD
 port (
   Q : out std_logic;
   D : in std_logic;
   G : in std_logic
 );
end component;
attribute syn_black_box of LD : component is true;
component LDC
 port (
   Q : out std_logic;
   CLR : in std_logic;
   D : in std_logic;
   G : in std_logic
 );
end component;
attribute syn_black_box of LDC : component is true;
component LDCE
 port (
   Q : out std_logic;
   CLR : in std_logic;
   D : in std_logic;
   G : in std_logic;
   GE : in std_logic
 );
end component;
attribute syn_black_box of LDCE : component is true;
component LDCE_1
 port (
   Q : out std_logic;
   CLR : in std_logic;
   D : in std_logic;
   G : in std_logic;
   GE : in std_logic
 );
end component;
attribute syn_black_box of LDCE_1 : component is true;
component LDCP
 port (
   Q : out std_logic;
   CLR : in std_logic;
   D : in std_logic;
   G : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of LDCP : component is true;
component LDCPE
 port (
   Q : out std_logic;
   CLR : in std_logic;
   D : in std_logic;
   G : in std_logic;
   GE : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of LDCPE : component is true;
component LDCPE_1
 port (
   Q : out std_logic;
   CLR : in std_logic;
   D : in std_logic;
   G : in std_logic;
   GE : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of LDCPE_1 : component is true;
component LDCP_1
 port (
   Q : out std_logic;
   CLR : in std_logic;
   D : in std_logic;
   G : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of LDCP_1 : component is true;
component LDC_1
 port (
   Q : out std_logic;
   CLR : in std_logic;
   D : in std_logic;
   G : in std_logic
 );
end component;
attribute syn_black_box of LDC_1 : component is true;
component LDE
 port (
   Q : out std_logic;
   D : in std_logic;
   G : in std_logic;
   GE : in std_logic
 );
end component;
attribute syn_black_box of LDE : component is true;
component LDE_1
 port (
   Q : out std_logic;
   D : in std_logic;
   G : in std_logic;
   GE : in std_logic
 );
end component;
attribute syn_black_box of LDE_1 : component is true;
component LDP
 port (
   Q : out std_logic;
   D : in std_logic;
   G : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of LDP : component is true;
component LDPE
 port (
   Q : out std_logic;
   D : in std_logic;
   G : in std_logic;
   GE : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of LDPE : component is true;
component LDPE_1
 port (
   Q : out std_logic;
   D : in std_logic;
   G : in std_logic;
   GE : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of LDPE_1 : component is true;
component LDP_1
 port (
   Q : out std_logic;
   D : in std_logic;
   G : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of LDP_1 : component is true;
component LD_1
 port (
   Q : out std_logic;
   D : in std_logic;
   G : in std_logic
 );
end component;
attribute syn_black_box of LD_1 : component is true;
component LUT1
 generic(INIT : bit_vector := "00");
 port (
   O : out std_logic;
   I0 : in std_logic
 );
end component;
attribute syn_black_box of LUT1 : component is true;
attribute xc_map of LUT1 : component is "lut";
component LUT1_D
 generic(INIT : bit_vector := "00");
 port (
   LO : out std_logic;
   O : out std_logic;
   I0 : in std_logic
 );
end component;
attribute syn_black_box of LUT1_D : component is true;
attribute xc_map of LUT1_D : component is "lut";
component LUT1_L
 generic(INIT : bit_vector := "00");
 port (
   LO : out std_logic;
   I0 : in std_logic
 );
end component;
attribute syn_black_box of LUT1_L : component is true;
attribute xc_map of LUT1_L : component is "lut";
component LUT2
 generic(INIT : bit_vector := X"0");
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic
 );
end component;
attribute syn_black_box of LUT2 : component is true;
attribute xc_map of LUT2 : component is "lut";
component LUT2_D
 generic(INIT : bit_vector := X"0");
 port (
   LO : out std_logic;
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic
 );
end component;
attribute syn_black_box of LUT2_D : component is true;
attribute xc_map of LUT2_D : component is "lut";
component LUT2_L
 generic(INIT : bit_vector := X"0");
 port (
   LO : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic
 );
end component;
attribute syn_black_box of LUT2_L : component is true;
attribute xc_map of LUT2_L : component is "lut";
component LUT3
 generic(INIT : bit_vector := X"00");
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of LUT3 : component is true;
attribute xc_map of LUT3 : component is "lut";
component LUT3_D
 generic(INIT : bit_vector := X"00");
 port (
   LO : out std_logic;
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of LUT3_D : component is true;
attribute xc_map of LUT3_D : component is "lut";
component LUT3_L
 generic(INIT : bit_vector := X"00");
 port (
   LO : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of LUT3_L : component is true;
attribute xc_map of LUT3_L : component is "lut";
component LUT4
 generic(INIT : bit_vector := X"0000");
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of LUT4 : component is true;
attribute xc_map of LUT4 : component is "lut";
component LUT4_D
 generic(INIT : bit_vector := X"0000");
 port (
   LO : out std_logic;
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of LUT4_D : component is true;
attribute xc_map of LUT4_D : component is "lut";
component LUT4_L
 generic(INIT : bit_vector := X"0000");
 port (
   LO : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of LUT4_L : component is true;
attribute xc_map of LUT4_L : component is "lut";
component MULT18X18
 port (
   P : out std_logic_vector(35 downto 0);
   A : in std_logic_Vector(17 downto 0);
   B : in std_logic_vector(17 downto 0)
 );
end component;
attribute syn_black_box of MULT18X18 : component is true;
component MULT18X18S
 port (
   P  : out std_logic_vector(35 downto 0);
   A  : in std_logic_Vector(17 downto 0);
   B  : in std_logic_vector(17 downto 0);
   C  : in std_logic;
   CE : in std_logic;
   R  : in std_logic
 );
end component;
attribute syn_black_box of MULT18X18S : component is true;
component MULT_AND
 port (
   LO : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic
 );
end component;
attribute syn_black_box of MULT_AND : component is true;
component MUXCY
 port (
   O : out std_logic;
   CI : in std_logic;
   DI : in std_logic;
   S : in std_logic
 );
end component;
attribute syn_black_box of MUXCY : component is true;
component MUXCY_D
 port (
   O : out std_logic;
   LO : out std_logic;
   CI : in std_logic;
   DI : in std_logic;
   S : in std_logic
 );
end component;
attribute syn_black_box of MUXCY_D : component is true;
component MUXCY_L
 port (
   LO : out std_logic;
   CI : in std_logic;
   DI : in std_logic;
   S : in std_logic
 );
end component;
attribute syn_black_box of MUXCY_