virtex2.vhd

FPGA-CPLD_DesignTool(8-9-10)源代码

 );
end component;
attribute syn_black_box of IBUF_HSTL_I_DCI : component is true;
component IBUF_HSTL_II
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_HSTL_II : component is true;
component IBUF_HSTL_II_DCI
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_HSTL_II_DCI : component is true;
component IBUF_HSTL_III
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_HSTL_III : component is true;
component IBUF_HSTL_III_DCI
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_HSTL_III_DCI : component is true;
component IBUF_HSTL_IV
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_HSTL_IV : component is true;
component IBUF_HSTL_IV_DCI
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_HSTL_IV_DCI : component is true;
component IBUF_LVCMOS15
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_LVCMOS15 : component is true;
component IBUF_LVCMOS18
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_LVCMOS18 : component is true;
component IBUF_LVCMOS2
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_LVCMOS2 : component is true;
component IBUF_LVCMOS25
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_LVCMOS25 : component is true;
component IBUF_LVCMOS33
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_LVCMOS33 : component is true;
component IBUF_LVDCI_15
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_LVDCI_15 : component is true;
component IBUF_LVDCI_18
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_LVDCI_18 : component is true;
component IBUF_LVDCI_25
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_LVDCI_25 : component is true;
component IBUF_LVDCI_33
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_LVDCI_33 : component is true;
component IBUF_LVDCI_DV2_15
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_LVDCI_DV2_15 : component is true;
component IBUF_LVDCI_DV2_18
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_LVDCI_DV2_18 : component is true;
component IBUF_LVDCI_DV2_25
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_LVDCI_DV2_25 : component is true;
component IBUF_LVDCI_DV2_33
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_LVDCI_DV2_33 : component is true;
component IBUF_LVTTL
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_LVTTL : component is true;
component IBUF_PCI33_3
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_PCI33_3 : component is true;
component IBUF_PCI66_3
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_PCI66_3 : component is true;
component IBUF_PCIX
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_PCIX : component is true;
component IBUF_SSTL2_I
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_SSTL2_I : component is true;
component IBUF_SSTL2_I_DCI
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_SSTL2_I_DCI : component is true;
component IBUF_SSTL2_II
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_SSTL2_II : component is true;
component IBUF_SSTL2_II_DCI
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_SSTL2_II_DCI : component is true;
component IBUF_SSTL3_I
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_SSTL3_I : component is true;
component IBUF_SSTL3_I_DCI
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_SSTL3_I_DCI : component is true;
component IBUF_SSTL3_II
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_SSTL3_II : component is true;
component IBUF_SSTL3_II_DCI
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_SSTL3_II_DCI : component is true;
component IFDDRCPE
 port (
   Q0  : out std_logic;
   Q1  : out std_logic;
   C0  : in std_logic;
   C1  : in std_logic;
   CE  : in std_logic;
   CLR : in std_logic;
   D   : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of IFDDRCPE : component is true;
component IFDDRRSE
 port (
   Q0 : out std_logic;
   Q1 : out std_logic;
   C0 : in std_logic;
   C1 : in std_logic;
   CE : in std_logic;
   D  : in std_logic;
   R  : in std_logic;
   S  : in std_logic
 );
end component;
attribute syn_black_box of IFDDRRSE : component is true;
component INV
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of INV : component is true;
component PIPEBUF
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of PIPEBUF : component is true;
component IOBUF
 generic (
   IOSTANDARD : string := "default";
   SLEW : string := "SLOW";
   DRIVE : integer := 12
 );
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF : component is true;
component IOBUFDS
 generic (
   IOSTANDARD : string := "default";
   SLEW : string := "SLOW";
   DRIVE : integer := 12
 );
 port (
   O : out std_logic;
   IO : inout std_logic;
   IOB : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUFDS : component is true;
component IOBUFDS_BLVDS_25
 port (
   O : out std_logic;
   IO : inout std_logic;
   IOB : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUFDS_BLVDS_25 : component is true;
component IOBUF_AGP
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_AGP : component is true;
component IOBUF_F_12
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_F_12 : component is true;
component IOBUF_F_16
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_F_16 : component is true;
component IOBUF_F_2
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_F_2 : component is true;
component IOBUF_F_24
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_F_24 : component is true;
component IOBUF_F_4
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_F_4 : component is true;
component IOBUF_F_6
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_F_6 : component is true;
component IOBUF_F_8
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_F_8 : component is true;
component IOBUF_GTL
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_GTL : component is true;
component IOBUF_GTL_DCI
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_GTL_DCI : component is true;
component IOBUF_GTLP
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_GTLP : component is true;
component IOBUF_GTLP_DCI
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_GTLP_DCI : component is true;
component IOBUF_HSTL_I
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_HSTL_I : component is true;
component IOBUF_HSTL_II
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_HSTL_II : component is true;
component IOBUF_HSTL_II_DCI
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_HSTL_II_DCI : component is true;
component IOBUF_HSTL_III
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_HSTL_III : component is true;
component IOBUF_HSTL_IV
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_HSTL_IV : component is true;
component IOBUF_HSTL_IV_DCI
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_HSTL_IV_DCI : component is true;
component IOBUF_LVCMOS15
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS15 : component is true;
component IOBUF_LVCMOS15_F_12
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS15_F_12 : component is true;
component IOBUF_LVCMOS15_F_16
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS15_F_16 : component is true;
component IOBUF_LVCMOS15_F_2
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS15_F_2 : component is true;
component IOBUF_LVCMOS15_F_4
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS15_F_4 : component is true;
component IOBUF_LVCMOS15_F_6
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS15_F_6 : component is true;
component IOBUF_LVCMOS15_F_8
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS15_F_8 : component is true;
component IOBUF_LVCMOS15_S_12
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS15_S_12 : component is true;
component IOBUF_LVCMOS15_S_16
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS15_S_16 : component is true;
component IOBUF_LVCMOS15_S_2
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS15_S_2 : component is true;
component IOBUF_LVCMOS15_S_4
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic