top.twr

FPGA-CPLD_DesignTool(8-9-10)源代码

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Release 6.2i Trace G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

C:/eda/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml top top.ncd -o
top.twr top.pcf


Design file:              top.ncd
Physical constraint file: top.pcf
Device,speed:             xc2v500,-6 (PRODUCTION 1.118 2004-03-12, STEPPING level 1)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock ipad_dll_clk_in
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
moda_data   |    1.363(R)|   -0.985(R)|clk_top           |   0.000|
modb_data   |    1.389(R)|   -1.011(R)|clk_top           |   0.000|
modc_data   |    1.367(R)|   -0.989(R)|clk_top           |   0.000|
top2a_c     |    3.023(R)|   -1.011(R)|clk_top           |   0.000|
top2b       |    1.389(R)|   -1.011(R)|clk_top           |   0.000|
------------+------------+------------+------------------+--------+

Clock ipad_dll_clk_in to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
moda_out    |    3.539(R)|clk_top           |   0.000|
modb_out    |    3.513(R)|clk_top           |   0.000|
modc_out    |    3.516(R)|clk_top           |   0.000|
------------+------------+------------------+--------+

Clock moda_clk_pad to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
obuft_out   |    5.995(R)|moda_clk          |   0.000|
------------+------------+------------------+--------+

Clock modb_clk_pad to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
obuft_out   |    9.345(R)|modb_clk          |   0.000|
------------+------------+------------------+--------+

Clock modc_clk_pad to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
mod_c_out   |    5.972(R)|modc_clk          |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock ipad_dll_clk_in
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
ipad_dll_clk_in|    3.509|         |         |         |
moda_clk_pad   |    5.529|         |         |         |
modb_clk_pad   |    5.039|         |         |         |
modc_clk_pad   |    5.243|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock moda_clk_pad
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
ipad_dll_clk_in|    4.314|         |         |         |
moda_clk_pad   |    4.079|         |         |         |
modc_clk_pad   |    2.298|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock modb_clk_pad
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
ipad_dll_clk_in|    2.536|         |         |         |
modb_clk_pad   |    2.036|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock modc_clk_pad
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
ipad_dll_clk_in|    3.271|         |         |         |
moda_clk_pad   |    2.501|         |         |         |
modb_clk_pad   |    1.995|         |         |         |
modc_clk_pad   |    2.549|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Wed Jun 02 03:29:15 2004
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Peak Memory Usage: 58 MB