cpldbus51.vhd

CPLD与8051的总线接口的VHDL设计源码及原理图和说明

--cpld 与8051的总线接口VHDL源码
--8051工作频率为11.0592MHZ  CPLD(EPM7128SLC15)的工作频率为16.0000MHZ(有源晶振)



library IEEE;
use IEEE.std_logic_1164.all;
use	IEEE.std_logic_unsigned.all;

entity cpldbus51 is
	port (										  
		Clk: in STD_LOGIC;		                   --Clock    16MHZ  
		Clr: in STD_LOGIC;						   --Clear	  high 
		P0: inout STD_LOGIC_VECTOR (7 downto 0);   --8052 Port 0
		P2: in STD_LOGIC_VECTOR (7 downto 0);	   --8052 Port 2
		ALE: in STD_LOGIC;                         --8052 ALE
--		PSEN: in STD_LOGIC;						   --8052'Psen
--		INT0:out  STD_LOGIC;                       --8052 INT0
		Wr: in STD_LOGIC;						   --8052'Wr
		Rd: in STD_LOGIC;						   --8052'Rd
---------------------------
		Pina:out	STD_LOGIC;                     ---output 
-----------------------
		nCS8255: out STD_LOGIC;				       --select 8255
		RamBank: out STD_LOGIC_VECTOR (1 downto 0);--Ram68128a bank switch   A15 A16
		nCsFlashRam: out STD_LOGIC;				   --select Flash Rom		 CE
		FlashRomBank: out STD_LOGIC_VECTOR (2 downto 0) --Flash Rom switch	 A14 A15 A16
	
	);
end cpldbus51;



architecture cpldbus51 of cpldbus51 is											
------------------------------------------------------------------------------
signal Addr: std_logic_vector(15 downto 0);		--16bit address
signal ALE_Sample:STD_LOGIC;
signal RamBankReg: STD_LOGIC_VECTOR (1 downto 0);--Ram bank switch reg, 4 banks, 4*32K=128k bytes
signal FlashRomBankReg: STD_LOGIC_VECTOR (2 downto 0);--Flash Rom bank switch reg, 8 banks, 8*16K=128k bytes
--Rd Sample
signal RdSample:std_logic;	--for Rd Sample
--WR Sample	
signal WrSample0:std_logic;	--Wr for Sample	
signal WrSample1:std_logic;	
signal WrSample2:std_logic;	
signal WrSample3:std_logic;
signal WrSample4:std_logic;	
signal WrSample5:std_logic;
--Wr Sample output
signal Wr_en:std_logic;	
--Clr Sample 
signal ClrSample0:std_logic;	-- for Clr Sample	
signal ClrSample1:std_logic;	
signal ClrSample2:std_logic;	
signal ClrSample3:std_logic;
signal ClrSample4:std_logic;	
signal ClrSample5:std_logic;
signal ClrSample6:std_logic;	
signal ClrSample7:std_logic;	
signal ClrSample8:std_logic;
signal ClrSample9:std_logic;	
--Clr Sample output
signal Clr_en:std_logic;
------------------------------------------------------------------------------
--output Reg
signal PinaReg:std_logic;  

begin	 
--------------------------------------------
--Sample Clr signal	 
ClrSample_p:process(Clk)
begin
	if Clk'event and Clk='1' then
		ClrSample0<=Clr;
		ClrSample1<=ClrSample0;
		ClrSample2<=ClrSample1;
		ClrSample3<=ClrSample2;
		ClrSample4<=ClrSample3;
		ClrSample5<=ClrSample4;
		ClrSample6<=ClrSample5;
		ClrSample7<=ClrSample6;
		ClrSample8<=ClrSample7;
		ClrSample9<=ClrSample8;
	end if;
end process;		 		 
---------------------------------------
--Clr Enable Signal
Clr_en_p:process(Clk)
begin		  
	if Clk'event and Clk='1' then
		if      ClrSample0='1' and ClrSample1='1'
			and ClrSample2='1' and ClrSample3='1'
			and ClrSample4='1' and ClrSample5='1'
			and ClrSample6='1' and ClrSample7='1'
			and ClrSample8='1' and ClrSample9='1' then
			Clr_en<='1';
		else
			Clr_en<='0';
		end if;
	end if;
end process;	   	  
------------------------------------------------
--sample ALE signal 
ALE_p:process(Clk)
	begin
		if Clk'event and Clk='1' then
			if Clr_en='1' then
				ALE_Sample<='0';
			else
				ALE_Sample<=ALE;
			end if;
		end if;
end process;
-------------------------------------------------			   
--Address Latch 
Address_p:process(Clk)
	begin
		if Clk'event and Clk='1' then
			if Clr_en='1' then
 				Addr<="0000000000000000";
			elsif ALE_Sample='1' then
				Addr<=P2&P0;
			end if;
		end if;
	end process;									   
-------------------------------------
--Sample Wr
WrSample_p:process(Clk)
begin
	if Clk'event and Clk='1' then
		if Clr_en='1' then
			WrSample0<='1';
			WrSample1<='1';
			WrSample2<='1';
			WrSample3<='1';
			WrSample4<='1';
			WrSample5<='1';
		else
			WrSample0<=Wr;
			WrSample1<=WrSample0;
			WrSample2<=WrSample1;
			WrSample3<=WrSample2;
			WrSample4<=WrSample3;
			WrSample5<=WrSample4;
		end if;
	end if;
end process;	
---------------------------------------
--internal Wr enable signal
WrEn_p:process(WrSample0,WrSample1,WrSample2,WrSample3,WrSample4,WrSample5)
begin
	if (WrSample0='0' and  WrSample1='0'
		and WrSample2='0' and WrSample3='0'
		and WrSample4='1'and WrSample5='1')then
		Wr_en<='1';
	else
		Wr_en<='0';
	end if;
end process;							
----------------------------------------
--Rd Sample
RdSample_p:process(Clk)
begin
	if Clk'event and Clk='1' then
		if Clr_en='1' then
			RdSample<='1';
		else
			RdSample<=Rd;
		end if;
	end if;
end process;
	
-----------------------------------
--Flash Rom Chip select signal
CS_Flash_p:process(Addr)
begin
	if Addr(15 downto 14)="10" then            --Address:8000h--BFFFh
	    nCsFlashRam<='0';
	else
		nCsFlashRam<='1';
	end if;
end process;
-----------------------------------
--	8255 Chip select signal
cs8255_p:process(Addr)
begin
		if Addr(15 downto 2)="11000000000000" then  --C000h--C003h	
			nCS8255<='0';
		else
			nCS8255<='1';
		end if;
	end process;			   
-----------------------------------
-----------------------------------	
-- Ram Bank Switch Reg	
Ram_bank_p:process(Clk)
begin				   
	if Clk'event and Clk='1' then
		if Clr_en='1' then
	   		RamBankReg<="00";		
		elsif Addr="1100000000000100" and Wr_en='1' then    --Address:C004h
	        RamBankReg<=P0(1 downto 0);
		end if;
	end if;
end process;
RamBank<=RamBankReg;  		   
----------------------------------
----------------------------------
--Flash Rom Switch Reg
Flash_bank_p:process(Clk)
begin					 
	if Clk'event and Clk='1' then
		if Clr_en='1' then
			FlashRomBankReg<="000";
		elsif Addr="1100000000000101"  and Wr_en='1' then      --Address:C005h
			FlashRomBankReg<=P0(2 downto 0);
		end if;
	end if;
end process;
FlashRomBank<=FlashRomBankReg;	  
--------------------------------
--------------------------------
--Rd process
-- now just two in-builde register
Rd_p:process(RdSample,Addr,RamBankReg,FlashRomBankReg)
begin
	if    Addr="1100000000000100"  and RdSample='0' then    --C004h
	    P0<="000000"&RamBankReg;
	elsif Addr="1100000000000101"  and RdSample='0' then    --C005h
		P0<="00000"&FlashRomBankReg;
	else	
		P0<="ZZZZZZZZ";
	end if;
end process;				
-------------------------------				
Pina_p:process(Clk)
begin
	if Clk'event and Clk='1' then
		if Clr_en='1' then
			PinaReg<='0';
		elsif Addr="1100000000000110"  and Wr_en='1' then      --C006h	
			PinaReg<=P0(0);
		end if;
	end if;
end process;	  
Pina<=PinaReg;			 
end cpldbus51;