singt.tan.rpt

产生正弦波波形的一个顶层文件

; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra0 ; DOUT[6] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra1 ; DOUT[6] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra2 ; DOUT[6] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra3 ; DOUT[6] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra4 ; DOUT[6] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra5 ; DOUT[6] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra0 ; DOUT[4] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra1 ; DOUT[4] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra2 ; DOUT[4] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra3 ; DOUT[4] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra4 ; DOUT[4] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra5 ; DOUT[4] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra0 ; DOUT[2] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra1 ; DOUT[2] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra2 ; DOUT[2] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra3 ; DOUT[2] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra4 ; DOUT[2] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra5 ; DOUT[2] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra0 ; DOUT[1] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra1 ; DOUT[1] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra2 ; DOUT[1] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra3 ; DOUT[1] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra4 ; DOUT[1] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra5 ; DOUT[1] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra0 ; DOUT[0] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra1 ; DOUT[0] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra2 ; DOUT[0] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra3 ; DOUT[0] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra4 ; DOUT[0] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra5 ; DOUT[0] ; CLK        ;
+-------+--------------+------------+----------------------------------------------------------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Dec 28 11:18:25 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off singt -c singt
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 125.0 MHz between source register "lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0]" and destination register "lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[5]"
    Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 3.100 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B12; Fanout = 11; REG Node = 'lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
            Info: 2: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = LC1_B12; Fanout = 3; COMB Node = 'lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT'
            Info: 3: + IC(0.000 ns) + CELL(0.300 ns) = 1.500 ns; Loc. = LC2_B12; Fanout = 3; COMB Node = 'lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT'
            Info: 4: + IC(0.000 ns) + CELL(0.300 ns) = 1.800 ns; Loc. = LC3_B12; Fanout = 3; COMB Node = 'lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT'
            Info: 5: + IC(0.000 ns) + CELL(0.300 ns) = 2.100 ns; Loc. = LC4_B12; Fanout = 3; COMB Node = 'lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT'
            Info: 6: + IC(0.000 ns) + CELL(0.300 ns) = 2.400 ns; Loc. = LC5_B12; Fanout = 1; COMB Node = 'lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT'
            Info: 7: + IC(0.000 ns) + CELL(0.700 ns) = 3.100 ns; Loc. = LC6_B12; Fanout = 9; REG Node = 'lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[5]'
            Info: Total cell delay = 3.100 ns ( 100.00 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 5.300 ns
                Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 59; CLK Node = 'CLK'
                Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC6_B12; Fanout = 9; REG Node = 'lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[5]'
                Info: Total cell delay = 2.800 ns ( 52.83 % )
                Info: Total interconnect delay = 2.500 ns ( 47.17 % )
            Info: - Longest clock path from clock "CLK" to source register is 5.300 ns
                Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 59; CLK Node = 'CLK'
                Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_B12; Fanout = 11; REG Node = 'lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
                Info: Total cell delay = 2.800 ns ( 52.83 % )
                Info: Total interconnect delay = 2.500 ns ( 47.17 % )
        Info: + Micro clock to output delay of source is 1.100 ns
        Info: + Micro setup delay of destination is 2.500 ns
Info: tco from clock "CLK" to destination pin "DOUT[3]" through memory "data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra0" is 30.000 ns
    Info: + Longest clock path from clock "CLK" to source memory is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 59; CLK Node = 'CLK'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = EC5_B; Fanout = 1; MEM Node = 'data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra0'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro clock to output delay of source is 0.600 ns
    Info: + Longest memory to pin delay is 24.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = EC5_B; Fanout = 1; MEM Node = 'data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra0'
        Info: 2: + IC(0.000 ns) + CELL(10.700 ns) = 10.700 ns; Loc. = EC5_B; Fanout = 1; MEM Node = 'data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[3]~mem_cell_ra0'
        Info: 3: + IC(0.000 ns) + CELL(2.500 ns) = 13.200 ns; Loc. = EC5_B; Fanout = 1; MEM Node = 'data_rom:u1|lpm_rom:lpm_rom_component|altrom:srom|q[3]'
        Info: 4: + IC(5.800 ns) + CELL(5.100 ns) = 24.100 ns; Loc. = PIN_24; Fanout = 0; PIN Node = 'DOUT[3]'
        Info: Total cell delay = 18.300 ns ( 75.93 % )
        Info: Total interconnect delay = 5.800 ns ( 24.07 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Dec 28 11:18:28 2006
    Info: Elapsed time: 00:00:04