alu_vlog_synpro.prj

FPGA-CPLD_DesignTool,事例程序1-2

#-- Synplicity, Inc.
#-- Version 7.0.2   
#-- Project file J:\Project_Navigator_Demo\alu_vlog\alu_vlog_synpro.prj
#-- Written on Thu Nov 07 20:32:54 2002


#add_file options
add_file -verilog "ALU.V"

#reporting options


#implementation: "alu_vlog_syn1"
impl -add alu_vlog_syn1

#device options
set_option -technology VIRTEX-E
set_option -part XCV50E
set_option -package CS144
set_option -speed_grade -8

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1

#map options
set_option -frequency 0.000
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -modular 0
set_option -retiming 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "alu_vlog_syn1/ALU.edf"
impl -active "alu_vlog_syn1"