alu_vlog.gfl

FPGA-CPLD_DesignTool,事例程序1-2

# Synplify flow : synCreateProject
__projnav/__synProj.rsp
alu.prj
__projnav/alu.ise_created
alu_compile.tcl
alu_map.tcl
# files created during Synthesis
stdout.log
stderr.log
alu.srs
alu.srm
alu.srr
j:/project_navigator_demo/alu_vlog/alu.edn
# Verilog : PDCL (jhdparse)
__projnav/ALU_jhdparse_tcl.rsp
# Verilog : PDCL (jhdparse)
__projnav/ALU_jhdparse_tcl.rsp
# Verilog : PDCL (jhdparse)
__projnav/ALU_jhdparse_tcl.rsp
# Synplify flow : synCreateProject
__projnav/__synProj.rsp
alu.prj
__projnav/alu.ise_created
alu_compile.tcl
alu_map.tcl
# files created during Synthesis
stdout.log
stderr.log
alu.srs
alu.srm
alu.srr
j:/project_navigator_demo/alu_vlog/alu.edn
# Verilog : PDCL (jhdparse)
__projnav/ALU_jhdparse_tcl.rsp
# Verilog : Create Schematic Symbol
__projnav/jhdparse.log
# ModelSim : Launch ModelSim Simulator
__projnav/vTOldo_tcl.rsp
alu.ldo
# ModelSim : Launch ModelSim Simulator
vsim.wlf
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
alu_tst_wave.vhw
alu_tst_wave.ano
alu_tst_wave.tfw
# ModelSim : Simulate Behavioral Verilog Model
__projnav/alu_tst_wave_createfdo.rsp
alu_tst_wave.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Verilog : View Verilog Instantiation Template
automake.err