alu_vlog.npl

来自「FPGA-CPLD_DesignTool,事例程序1-2」· NPL 代码 · 共 20 行

JDF F
// Created by Project Navigator ver 1.0
PROJECT alu_vlog
DESIGN alu_vlog Normal
DEVFAM virtexe
DEVFAMTIME 0
DEVICE xcv50e
DEVICETIME 0
DEVPKG cs144
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
FLOW Synplify Pro Verilog
FLOWTIME 1036657229
STIMULUS alu_tst_wave.tbw Normal
MODULE ALU.V
MODSTYLE alu Normal
[STRATEGY-LIST]
Normal=True