alu.srs

FPGA-CPLD_DesignTool,事例程序1-2

#
#
#
# Created by Synplify Verilog HDL Compiler version 7.0.0, Build 130R from Synplicity, Inc.
# Copyright 1994-1999 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Fri Nov 08 09:08:25 2002
#
#
#OPTIONS:"|-top|alu|-ram|-primux|-fixsmult|-infer_seqShift|-Ij:\\eda\\synplicity\\Synplify_70\\lib|-autosm|-fid2|-sharing|on|-encrypt|-ui"
#CUR:"j:\\eda\\synplicity\\Synplify_70\\bin\\c_ver.exe":1005881054l
#CUR:"J:\\Project_Navigator_Demo\\alu_vlog\\ALU.V":1036717701l
f "J:\Project_Navigator_Demo\alu_vlog\ALU.V"; # file 0
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