alu.sym

来自「FPGA-CPLD_DesignTool,事例程序1-2」· SYM 代码 · 共 49 行

VERSION 5
BEGIN SYMBOL 
SYMBOLTYPE BLOCK
TIMESTAMP 2002 12 19 9 46 25
SYMATTR VeriModel "alu"
SYMPIN 0 -224 Input "clk"
SYMPIN 0 -160 Input "a(7:0)"
SYMPIN 0 -96 Input "b(7:0)"
SYMPIN 0 -32 Input "opcode(2:0)"
SYMPIN 528 -224 Output "outp_s(7:0)"
SYMPIN 528 -32 Output "outp_a(7:0)"
RECTANGLE N 64 -256 464 0 
BEGIN DISPLAY 264 -264 ATTR "SymbolName"
    ALIGNMENT BCENTER
    FONT 56 "Arial"
END DISPLAY
LINE N 64 -224 0 -224 
BEGIN DISPLAY 72 -224 PIN "clk" ATTR "PinName"
    FONT 24 "Arial"
END DISPLAY
LINE N 64 -160 0 -160 
BEGIN DISPLAY 72 -160 PIN "a(7:0)" ATTR "PinName"
    FONT 24 "Arial"
END DISPLAY
RECTANGLE N 0 -172 64 -148 
LINE N 64 -96 0 -96 
BEGIN DISPLAY 72 -96 PIN "b(7:0)" ATTR "PinName"
    FONT 24 "Arial"
END DISPLAY
RECTANGLE N 0 -108 64 -84 
LINE N 64 -32 0 -32 
BEGIN DISPLAY 72 -32 PIN "opcode(2:0)" ATTR "PinName"
    FONT 24 "Arial"
END DISPLAY
RECTANGLE N 0 -44 64 -20 
LINE N 464 -224 528 -224 
BEGIN DISPLAY 456 -224 PIN "outp_s(7:0)" ATTR "PinName"
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
RECTANGLE N 464 -236 528 -212 
LINE N 464 -32 528 -32 
BEGIN DISPLAY 456 -32 PIN "outp_a(7:0)" ATTR "PinName"
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
RECTANGLE N 464 -44 528 -20 
END SYMBOL