alu.plg

来自「FPGA-CPLD_DesignTool,事例程序1-2」· PLG 代码 · 共 17 行

@P:  Worst Slack : 991.640
@P:  clk - Estimated Frequency : 357.1 MHz
@P:  clk - Requested Frequency : 1.0 MHz
@P:  clk - Estimated Period : 2.800
@P:  clk - Requested Period : 1000.000
@P:  clk - Slack : 997.200
@P:  System - Estimated Frequency : 119.6 MHz
@P:  System - Requested Frequency : 1.0 MHz
@P:  System - Estimated Period : 8.360
@P:  System - Requested Period : 1000.000
@P:  System - Slack : 991.640
@P: alu Part : xcv50ecs144-8
@P: alu I/O primitives : 35
@P: alu I/O Register bits : 8
@P: alu Register bits (Non I/O) : 0 (0%)
@P: alu Total Luts : 26 (1%)